1
John D Hall, Alfred S Williams Jr: Simulator control loading inertia compensator. The Singer Company, J Dennis Moore, Richard J Paciulan, Jeff Rothenberg, December 2, 1980: US04236325 (227 worldwide citation)

Signals are developed representative of the mechanical inertia of a vehicle simulator linkage elements that drive control members utilized by a student operator. These signals are combined with signals representative of programmed vehicle operating data and signals representative of the student oper ...


2
Jean Christophe E Cuenod, Peter A Sichel: Computer peripheral device network with peripheral address resetting capabilities. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, May 31, 1994: US05317693 (193 worldwide citation)

A desktop communications network connects numerous peripheral devices to a host computer via a single host interface. The host interface and each peripheral device's interface has its own CPU, with software for assigning each peripheral device a unique address. The bus interface associated with each ...


3
Rebecca L Stamm, John Edmondson, David Archer, Samyojita Nadkarni, Raymond Strouble: Processor system with writeback cache using writeback and non writeback transactions stored in separate queues. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, May 31, 1994: US05317720 (114 worldwide citation)

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full ...


4
Hamid Partovi, William R Wheeler, Michael Leary, Michael A Case, Steven Butler, Rajesh Khanna: Fast tag compare and bank select in set associative cache. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, October 4, 1994: US05353424 (67 worldwide citation)

A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed ...


5
Fred Horwitz, Eric Thomas: Method of packaging and assembling opto-electronic integrated circuits. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, December 6, 1994: US05371822 (54 worldwide citation)

A method of constructing opto-electronic integrated circuit packages passively aligns optical fibers inserted through holes in a package lid which are arranged in a pattern which corresponds with the pattern of emitters and receivers on a circuit die. When the lid is aligned with a package base to w ...


6
Warren L Saltz, Anthony S Vezza: Method and apparatus for disabling and diagnosing cache memory storage locations. Digital Equipment Corporation, Arthur W Fisher, Richard J Paciulan, November 2, 1982: US04357656 (43 worldwide citation)

In a data processing system having a main memory containing addressable main memory storage locations, and also having a processor with a cache memory containing addressable cache memory storage locations, signals representative of predetermined addressable cache memory storage locations desired to ...


7
Raj Ramanujan: Apparatus and method for ensuring that lock requests are serviced in a multiprocessor system. Digital Equipment Corporation, Richard J Paciulan, Denis C Maloney, August 23, 1994: US05341491 (41 worldwide citation)

A lockout avoidance circuit is provided for a plurality of nodes which generate lock requests for a shared resource such as a memory location. The circuit insures that lock requests are eventually satisfied. A lock queue includes a plurality of registers pipelined together. Lock requests only enter ...


8
John Croll: Boot system for distributed digital data processing system. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, November 22, 1994: US05367688 (39 worldwide citation)

A distributed digital data processing system including a host and at least one node interconnected by a communications link. In response to a boot command, the node requests its boot image from the host over the communications link. The host then provides pointers to portions of the boot image to th ...


9
Colyn Case, Kim Meinerth, John Irwin, Blaise Fanning: Graphics command processing method in a computer graphics system. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, Clayton L Satow, May 24, 1994: US05315696 (36 worldwide citation)

In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. A separate translator provides conversion from generated virtual addresses to physical addresses. The address generator formulates addresses as a function of distance from the ori ...


10
Sharon M Britton, Randy Allmon, Sridhar Samudrala: Leading one/zero bit detector for floating point operation. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, May 31, 1994: US05317527 (35 worldwide citation)

A circuit is provided for using the input operands of a floating point addition or subtraction operation to detect the leading one or zero bit position in parallel with the arithmetic operation. This allows the alignment to be performed on the available result in the next cycle of the floating point ...