1
James Thomas Brady, Jaishankar Moothedath Menon: Failure prediction for disk arrays. International Business Machines Corporation, Raymond M Jenkens & Gilchrist Galasso, Ingrid M Foerster, March 10, 1998: US05727144 (75 worldwide citation)

In a data processing system employing a disk array, prediction of a possible failure of a disk drive initiates copying of the data away from the potentially failing disk drive to a spare disk drive before the failing drive actually fails. If the disk drive does fail before the copying of the content ...


2
Dan M Neal, Edward J Silha, Steven M Thurber: Data processing system including buffering mechanism for inbound and outbound reads and posted writes. International Business Machines Corporation, Raymond M Jenkens & Gilchrist Galasso, Anthony V S England, December 2, 1997: US05694556 (50 worldwide citation)

A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bus to bus bridge connects between a primary bus and a secondary bus whe ...


3
Damon W Finney, Michael James Rayfield: Method and apparatus for testing links between network switches. International Business Machines Corporation, Raymond M Jenkens & Gilchrist Galasso, Leslie G Murray, January 27, 1998: US05712856 (24 worldwide citation)

A test link protocol which continuously monitors each link in a network to ensure that the link is correctly transmitting data. Each switch, or torus has at least one of two functional components: Send Test and Receive Test. The Send Test component monitors control codes at a torus link output. The ...


4
Stephen Larry Runyon, Eric Bernard Schorn: Data processing system and method for improving performance of domino-type logic using multiphase clocks. International Business Machines Corporation, Raymond M Jenkens & Gilchrist Galasso, Anthony V S England, July 8, 1997: US05646557 (17 worldwide citation)

A domino logic circuit includes an evaluation circuit for receiving input signals and performing a logic operation on the input signals, a passgate circuit for controlling the transmission of signals to an output circuit and a feedback latch circuit for holding the output of the evaluation circuit f ...


5
Amy Chang, Hui I Hsiao, Anant D Jhingran, Walter Gene Wilson: Method and system for avoiding blocking in a data processing system having a sort-merge network. International Business Machines Corporation, Raymond M Jenkens & Gilchrist Galasso, Richard P Ludwin, October 21, 1997: US05680608 (11 worldwide citation)

In a system having producer and consumer processes, a producing process look ahead in its outgoing data stream to ensure that there is data available to consumers on all outgoing streams. The producer looks ahead by keeping a data array in its memory space with an entry for each connected consumer. ...


6
Tom Tien Cheng Chiu, Donald George Mikan Jr, John Stephen Muhich: Comparator circuit using two bit to four bit encoder. International Business Machines Corporation, Raymond M Jenkens & Gilchrist Galasso, Anthony V S England, September 16, 1997: US05668525 (8 worldwide citation)

Comparative circuits 10, 100 for comparing a first address comprising at least two bits to a second address comprising an equal number of corresponding bits as the first address to determine if the first address equals or does not equal the second address as disclosed. Comparative circuits 10, 100 i ...


7
Paul Chang, Roch A Guerin, Abhay Kumar Parekh, James Thomas Rayfield: Method and system for implementing multiple leaky bucket checkers using a hybrid synchronous/asynchronous update mechanism. International Business Machines Corporation, Raymond M Jenkens & Gilchrist Galasso, Christian Heusch, November 10, 1998: US05835711 (7 worldwide citation)

A leaky bucket checker which combines synchronous updates with event driven asynchronous updates triggered by packet arrivals. A synchronous update is performed exactly as an event-driven update by assuming that a packet of length zero has arrived at the time of the update. These updates are perform ...


8
Giordano Seragnoli: Multiple function battery charger, self-configuring as supply voltage regulator for battery powered apparatuses. SGS Thomson Microelectronics S r 1, Raymond M Jenkens & Gilchrist Galasso, Alberto Pellegri, April 7, 1998: US05736832 (7 worldwide citation)

Regulation of the output supply voltage to a load powered by a rechargeable battery of a portable apparatus, typically a telephone, is advantageously implemented by exploiting the switching STEP-DOWN REGULATOR of an in-built battery charger. The regulator circuit configures itself in function of the ...


9
Ravi Kumar Arimilli, John Steven Dodson, Guy Lynn Guthrie, Jerry Don Lewis: Data processing system having demand based write through cache with enforced ordering. International Business Machines Corporation, Raymond M Jenkens & Gilchrist Galasso, Anthony V S England, August 18, 1998: US05796979 (6 worldwide citation)

A data processing system includes a processor, a system memory, one or more input/output channel controllers (IOCC), and a system bus connecting the processor, the memory and the IOCCs together for communicating instructions, address and data between the various elements of a system. The IOCC includ ...


10
Gilles Gervais, Ingemar Holm, Helmut Kohler, Thomas Koehler, Norbert Schumacher, Gerhard Zilles: Checking data integrity in buffered data transmission. International Business Machines Corporation, Raymond M Jenkens & Gilchrist Galasso, Arthur J Samodovitz, December 2, 1997: US05694400 (1 worldwide citation)

Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) betwee ...