1
Walford W Ho, Chao Chiang Chen, Yuk Y Yang: Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array. Intelligent Logic Systems, Phong K Fenwick & West Truong, October 3, 1995: US05455525 (329 worldwide citation)

A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includ ...


2
Chih Wei D Chang, Nirmal Saxena: Fault tolerant address translation method and system. HaL Computer Systems, Phong K Fenwick & West Truong, October 3, 1995: US05455834 (56 worldwide citation)

A method and system are disclosed wherein error detection codes are used for detecting and handling hardware errors in a memory table. Before each address and associated data are entered into the memory table, an error detection code is generated for both the address and the data. The address, data, ...