1
Ross H Freeman, Hung Cheng Hsieh: Distributed memory architecture for a configurable logic array and method for using distributed memory. Xilinx, Edel M Young, Patrick T Bever, August 30, 1994: US05343406 (252 worldwide citation)

Additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array ...


2
Ralph D Wittig, Sundararajarao Mohan, Richard A Carberry: FPGA configurable logic block with multi-purpose logic/memory circuit. Xilinx, Patrick T Bever Hoffman & Harms Bever Esq, Lois D Cartier, November 21, 2000: US06150838 (247 worldwide citation)

A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen p ...


3
Stephen M Trimberger: Method for making large-scale ASIC using pre-engineered long distance routing structure. Xilinx, Patrick T Bever, H C Chan, Edel M Young, July 29, 2003: US06601227 (247 worldwide citation)

Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is res ...


4
David P Schultz, Lawrence C Hung, F Erich Goetting: Method and structure for configuring FPGAS. Xilinx, Patrick T Bever Esq, Lois D Cartier, Bever Hoffman & Harms, March 20, 2001: US06204687 (193 worldwide citation)

An FPGA configuration circuit including a bus interface for applying a bit stream from either a JTAG interface or an input/output block (IOB) interface onto a bus. The bus interface parses a header word from the bit stream into an address field and an operand field. Several registers are connected t ...


5
Yacov Malinovich, Ephie Koltin: Method for making backside illuminated image sensor. Tower Semiconductor, Patrick T Bever, Bever Hoffman & Harms, January 2, 2001: US06168965 (188 worldwide citation)

A method for producing a back-illuminated CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. The semiconductor substrate is secured to a protective substrate by an adhesive such that the processed (frontside) surface of the semicon ...


6
Sundararajarao Mohan: On-chip self-modification for PLDs. Xilinx, Patrick T Bever, July 3, 2001: US06255849 (179 worldwide citation)

An on-chip method for self-modifying a programmable logic device (PLD) including a plurality of configurable logic blocks (CLBs), a plurality of interconnect resources for selectively connecting the CLBs, and a block memory circuit selectively connected to the interconnect resources. The CLBs are co ...


7
Ichiro Morishita, Yuichi Yasuda, Yuichi Umeda, Arao Sato, Junichi Saito, Masahiro Tanaka, Tomomitsu Muta, Masatoshi Uchio, Kazuhiro Katagiri, Masaru Nakayama: Space coordinates detecting device and input apparatus using same. Alps Electric, Guy W Shoup, Patrick T Bever, May 6, 1997: US05627565 (169 worldwide citation)

According to the present invention there is provided a space coordinates detecting device wherein a detecting section for detecting light emitted from a light source is provided, thereby permitting detection of a relative angle between a light emitting sections and the detecting section and hence pe ...


8
Yacov Malinovich, Ephie Koltin: Backside illuminated image sensor. Tower Semiconductor, Patrick T Bever, Bever Hoffman & Harms, January 2, 2001: US06169319 (161 worldwide citation)

A method for producing a back-illuminated CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. The semiconductor substrate is secured to a protective substrate by an adhesive such that the processed (frontside) surface of the semicon ...


9
Kamal Chaudhary, Sudip K Nag: Post-placement residual overlap removal method for core-based PLD programming process. Xilinx, Patrick T Bever Esq, Jeanette S Harms Esq, July 11, 2000: US06086631 (153 worldwide citation)

A post-placement residual overlap removal process for use with core-based programmable logic device programming methods that is called when an optimal placement solution includes one or more overlapping cores. Horizontal and vertical constraint graphs are utilized to mathematically define the two-di ...


10
David A Harrison, Joshua M Silver, Soren T Soe: Method for programming complex PLD having more than one function block type. Xilinx, Patrick T Bever, Jeanette S Harms, October 5, 1999: US05963048 (146 worldwide citation)

A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing bo ...