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Sinclair Alan Welsh, Gorobets Sergey Anatolievich, Bennett Alan David, Smith Peter John: Non-volatile memory and method with non-sequential update block management. Sandisk Corporation, Sinclair Alan Welsh, Gorobets Sergey Anatolievich, Bennett Alan David, Smith Peter John, PARSONS Gerald P, July 21, 2005: WO/2005/066793 (38 worldwide citation)

In a nonvolatile memory with block management system that supports update blocks with non-sequential logical units, an index of the logical units in a non-sequential update block is buffered in RAM and stored periodically into the non-volatile memory. In one embodiment, the index is stored in a bloc ...


2
Gonzalez Carlos J, Conley Kevin M: Flash memory data correction and scrub techniques. Sandisk Corporation, Gonzalez Carlos J, Conley Kevin M, PARSONS Gerald P, April 21, 2005: WO/2005/036401 (26 worldwide citation)

In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The someti ...


3
Cuellar Edwin J, Harari Eliyahou, Miller Robert C, Takiar Hem P, Wallace Robert F: Memory cards having two standard sets of contacts. Sandisk Corporation, Cuellar Edwin J, Harari Eliyahou, Miller Robert C, Takiar Hem P, Wallace Robert F, PARSONS Gerald P, November 10, 2005: WO/2005/106781 (20 worldwide citation)

Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a memory card standard and that of th ...


4
Gorobets Sergey Anatolievich: Managing housekeeping operations in flash memory. Sandisk Corporation, Gorobets Sergey Anatolievich, PARSONS Gerald P, December 4, 2008: WO/2008/147752 (19 worldwide citation)

A flash re-programmable, non-volatile memory system is operated to disable foreground execution of housekeeping operations, such as wear leveling and data scrub, in the when operation of the host would be excessively slowed as a result. One or more characteristics of patterns of activity of the host ...


5
Cernea Raul Adrian, Li Yan, Mofidi Mehrdad, Khalid Shahzad: Non-volatile memory and method with bit line to bit line coupled compensation. Sandisk Corporation, Cernea Raul Adrian, Li Yan, Mofidi Mehrdad, Khalid Shahzad, PARSONS Gerald P, March 31, 2005: WO/2005/029502 (17 worldwide citation)

When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention pro ...


6
Cernea Raul Adrian: Memory sensing circuit and method for low voltage operation. Sandisk Corporation, Cernea Raul Adrian, PARSONS Gerald P, June 22, 2006: WO/2006/065501 (16 worldwide citation)

A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line coupling. The rate of discharge of a dedicated capacitor as measured by a change in the voltage drop therea ...


7
Gonzalez Carlos J, Conley Kevin M: Automated wear leveling in non-volatile storage systems. Sandisk Corporation, PARSONS Gerald P, May 13, 2004: WO/2004/040586 (16 worldwide citation)

Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first ...


8
Li Yan: Non-volatile memory with background data latch caching during program operations and methods therefor. Sandisk Corporation, Li Yan, PARSONS Gerald P, November 15, 2007: WO/2007/130976 (14 worldwide citation)

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching an ...


9
Lin Jason, Li Yan: Non-volatile memory with background data latch caching during erase operations and methods therefor. Sandisk Corporation, Lin Jason, Li Yan, PARSONS Gerald P, November 15, 2007: WO/2007/131059 (14 worldwide citation)

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching an ...


10
Li Yan: Non-volatile memory with background data latch caching during read operations and methods therefor. Sandisk Corporation, Li Yan, PARSONS Gerald P, November 15, 2007: WO/2007/131062 (14 worldwide citation)

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching an ...