41
Thomas O Holtey: I/O Request interrupt mechanism. Honeywell Information Systems, Nicholas Prasinos, September 22, 1981: US04291371 (53 worldwide citation)

Apparatus for intercepting a channel program that is operative with a particular input/output device when an input/output device of higher priority requests service. The channel program is intercepted at a time when the processor is required to process a minimum of information. This enables the proc ...


42
Charles W Bachman, Jacques Bouvard: Extended semaphore architecture. Honeywell Information Systems, Nicholas Prasinos, March 16, 1982: US04320451 (53 worldwide citation)

A generalized event management architecture based upon an analysis of the traditional interprocess communication and synchronization mechanisms is disclosed. An extended semaphore architecture is proposed which combines the properties of Dijkstra's semaphore with that of a trap facility. This model ...


43
Roger L Hall, Domenic R Romano: Cathode ray tube display terminal having an enclosure for protection of a logic board. Honeywell Information Systems, George Grayson, Nicholas Prasinos, June 14, 1983: US04388671 (52 worldwide citation)

A cathode ray tube display terminal includes a printed circuit logic board permanently mounted in a molded plastic enclosure assembly during "on the shelf" storage and shipment of the enclosure as a spare part and during normal operation of the CRT display terminal. The enclosure assembly includes a ...


44
Charles W Bachman, Benjamin S Franklin: Database instruction unload. Honeywell Information Systems, Nicholas Prasinos, Ronald T Reiling, August 23, 1977: US04044334 (50 worldwide citation)

One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction which determines the appropriate register where a database pointer is currently stored, ...


45
Daniel A Boudreau: Data processing system auto address development logic for multiword fetch. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, April 16, 1985: US04511960 (50 worldwide citation)

An auto address development logic that, when provided a starting address, is used to develop consecutive addresses as multiple words of information are presented, one word at a time, during multiple consecutive information transfer cycles. The logic retains for use a current address while simultaneo ...


46
Laurie J Leger: Universal snap-in card guide for printed circuit card enclosures. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, May 4, 1982: US04327835 (50 worldwide citation)

A printed circuit card enclosure is disclosed having end plates and shelf members which are secured together to form the enclosure. The shelf members are provided with holes for receiving flexible snap-in card guides which are used to retain and support printed cards within the enclosure. The shelf ...


47
Robert C Beauchesne, Robert J Russell: Embedded memory testing method and apparatus. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, November 6, 1984: US04481627 (50 worldwide citation)

A method for testing memory arrays embedded within electronic assemblies having other combinatorial logic elements connected to the inputs thereof. By following stated design rules, the embedded memory can be isolated from the combinatorial logic element and tested by use of a memory test subsystem ...


48
Charles W Bachman: Data processing system utilizing data field descriptors for processing data files. Honeywell Information Systems, William W Holloway Jr, Ronald T Reiling, Nicholas Prasinos, January 10, 1978: US04068300 (50 worldwide citation)

A data field descriptor extends the flexibility of operand accesses by defining the attributes of a data field with regard to length, location and form of data representation at execution time. This delay of binding the operand accesses until execution time supports both data independence and securi ...


49
Daniel A Boudreau, Edward R Salas: Priority resolver having dynamically adjustable priority levels. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, January 8, 1985: US04493036 (50 worldwide citation)

A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main ...


50
James W Keeley, Edwin P Fisher, John L Curley: Multilevel cache system with graceful degradation capability. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, August 7, 1984: US04464717 (48 worldwide citation)

The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting ...