1
Pradeep Yelehanka, Tong Qing Chen, Zhi Yong Han, Zhen Jia Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah: Method of manufacturing semiconductor local interconnect and contact. Chartered Semiconductor Manufacturing, Mikio Ishimaru, April 26, 2005: US06884712 (184 worldwide citation)

An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped sp ...


2
Madhu Rayabhari: Configurable universal serial bus node. Fairchild Semiconductor Corporation, Mikio Ishimaru, March 28, 2000: US06044428 (163 worldwide citation)

A Universal Serial Bus node having a non-volatile memory is preprogrammed with the data bits necessary to configure an attached state machine to become a translator or modified translator for signals from a computer peripheral device. On startup, the Universal Serial Bus node is configured to transl ...


3
Sergey D Lopatin, Shekhar Pramanick, Dirk Brown: Semiconductor metalization barrier. Advanced Micro Devices, Mikio Ishimaru, November 7, 2000: US06144099 (156 worldwide citation)

A semiconductor metalization barrier, and manufacturing method therefor, is provided which is a stack of a cobalt layer and cobalt tungsten layer deposited on a copper bonding pad.


4
Kouros Ghandehari, Jean Y Yang, Christopher A Spence: Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types. Advanced Micro Devices, Mikio Ishimaru, February 7, 2006: US06994939 (154 worldwide citation)

A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the ...


5
Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow, Byung Joon Han: Stacked semiconductor packages and method for the fabrication thereof. ST Assembly Test Services, Mikio Ishimaru, March 1, 2005: US06861288 (149 worldwide citation)

A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A sec ...


6
Sergey D Lopatin, Shekhar Pramanick, Dirk Brown: Manufacturing method for semiconductor metalization barrier. Advanced Micro Devices, Mikio Ishimaru, February 5, 2002: US06344410 (144 worldwide citation)

A semiconductor metalization barrier, and manufacturing method therefor, is provided which is a stack of a cobalt layer and cobalt tungsten layer deposited on a copper bonding pad.


7
Matthew R Gibbons, Marcos Lederman: Dual, synthetic spin valve sensor using current pinning. Read Rite Corporation, Mikio Ishimaru, July 9, 2002: US06418000 (143 worldwide citation)

A dual symmetric spin valve sensor consists of outer ferromagnetic pinned layers which are pinned by a current induced magnetic field. One of the outer pinned layers is magnetically coupled to an inner pinned layer which is pinned so that the magnetization of the other outer and the inner pinned lay ...


8
Zhupei Shi, Ming Mao, Qunwen Leng: Read sensor with improved thermal stability and manufacturing method therefor. Read Rite Corporation, Mikio Ishimaru, August 21, 2001: US06277505 (141 worldwide citation)

A structure which includes a ferromagnetic (FM) layer, a thin oxide layer, and an antiferromagnetic (AFM) layer is provided. The thin oxide layer, between 1 to 10 oxygen atoms in thickness, minimizes interlayer atomic diffusion between the FM layer and the antiferromagnetic layer. In a preferred emb ...


9
Robert A Bigler: Panel and trade show booth made therefrom. Mikio Ishimaru, April 29, 2003: US06553724 (139 worldwide citation)

A panel is provided, which is a building block, for a trade show booth. Each panel includes a support structure having rails secured to the edges. Each rail has magnetic fastening strips and metal guidance blades disposed in the lengthwise extending slots, which engage with similar structures in oth ...


10
Geoffrey Choh Fei Yeap, Qi Xiang, Ming Ren Lin: CMOS optimization method utilizing sacrificial sidewall spacer. Advanced Micro Devices, Mikio Ishimaru, July 25, 2000: US06093594 (133 worldwide citation)

An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and ...