1
Xavier Baie
Brent A Anderson, Xavier Baie, Randy W Mann, Edward J Nowak, Jed H Rankin: High mobility transistors in SOI and method for forming. International Business Machines Corporation, Mark F Chadurjian, Schmeiser Olsen & Watts, September 23, 2003: US06624478 (25 worldwide citation)

The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been ...


2
David M Fried, Edward J Nowak, Beth A Rainey, Devendra K Sadana: Fin FET devices from bulk semiconductor and method for forming. International Business Machines Corporation, Mark F Chadurjian, Schmeiser Olsen & Watts, November 4, 2003: US06642090 (292 worldwide citation)

The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while ...


3
Roy S Bass Jr, Arup Bhattacharyya, Gary D Grise: Non-volatile memory cell having Si rich silicon nitride charge trapping layer. International Business Machines Corporation, Mark F Chadurjian, September 26, 1989: US04870470 (224 worldwide citation)

A non-volatile storage cell comprising a field effect transistor having source, gate, and drain electrodes. The gate electrode includes a gate stack having a dielectric layer, a charge storage structure comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide ap ...


4
William J Cote, Donald M Kenney, Michael L Kerbaugh, Michael A Leach, Jeffrey A Robinson, Robert W Sweetser: Process for defining organic sidewall structures. International Business Machines Corporation, Mark F Chadurjian, June 13, 1989: US04838991 (217 worldwide citation)

A conformal organic layer is used to define spacers on the sidewalls of an organic mandrel. The organic layer (e.g., parylene) can be deposited at low temperatures, and as such is compatible with temperature-sensitive mandrel materials that reflow at high deposition temperatures. The conformal organ ...


5
Ramachandra Divakauni, Mark C Hakey, William H L Ma, Jack A Mandelman, William R Tonti: SOI stacked DRAM logic. International Business Machines Corporation, Mark F Chadurjian, Whitman Curtis & Christofferson P C, April 8, 2003: US06544837 (202 worldwide citation)

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal ...


6
Arup Bhattacharyya, Michael L Kerbaugh, Robert M Quinn, Jeffrey A Robinson: Formation of variable-width sidewall structures. International Business Machines Corporation, Mark F Chadurjian, October 11, 1988: US04776922 (184 worldwide citation)

Spacers are formed having widths that vary as a function of the spacing between the mandrels upon which the conformal material that defines the spacers is deposited and etched. As the spacing between adjacent mandrels decreases, the width of the resulting spacers decreases. The correlation between m ...


7
Robert Michael Geffken, William Thomas Motsiff, Ronald R Uttecht: Personalization structure for semiconductor devices. International Business Machines Corporation, Mark F Chadurjian, Schmeiser Olsen & Watts, March 16, 1999: US05883435 (161 worldwide citation)

The preferred embodiment of the present invention provides a structure and method for personalizing a semiconductor device in the context of a bump array connection to packaging, substrates and such. The preferred embodiment method uses a plurality of conduction lines on said semiconductor device, i ...


8
William F Clark, David M Fried, Louis D Lanzerotti, Edward J Nowak: Strained fin FETs structure and method. International Business Machines Corporation, Mark F Chadurjian Esq, McGinn & Gibb PLLC, October 21, 2003: US06635909 (145 worldwide citation)

A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structur ...


9
William J Cote, Carter W Kaanta, Michael A Leach, James K Paulsen: Via-filling and planarization technique. International Business Machines Corporation, Mark F Chadurjian, September 11, 1990: US04956313 (137 worldwide citation)

A method of forming a plurality of conductive studs within a non-planar insulator layer (e.g., PSG or BPSG) disposed between a first series of conductive structures arranged on a substrate and metal lines formed on the upper surface of the insulator layer. Vertical vias are defined through the insul ...


10
David M Fried, Timothy J Hoague, Edward J Nowak, Jed H Rankin: Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same. International Business Machines Corporation, Mark F Chadurjian Esq, Scully Scott Murphy & Presser, June 24, 2003: US06583469 (135 worldwide citation)

A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a source region and a drain region. The channel region has a first horizontal width and the source and dr ...



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