1
Eric N Mann, John Q Torode: Programmable clock generator. Cypress Semiconductor, Christopher P Maiorana, Maiorana & Acosta P C, March 2, 1999: US05877656 (121 worldwide citation)

A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of va ...


2
Galen E Stansell: Enabling clock signals with a phase locked loop (PLL) lock detect circuit. Cypress Semiconductor, Maiorana & Acosta P C, March 23, 1999: US05886582 (88 worldwide citation)

A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase locked relative to an input reference signal ...


3
Edward L Grivna, Paul Scott: Minimum-latency data mover with auto-segmentation and reassembly. Cypress Semiconductor, Maiorana & Acosta P C, September 7, 1999: US05949799 (73 worldwide citation)

A data mover which provides guaranteed transfer of data between two locations. The data mover includes a pair of data packet memories for input, a pair of data packet memories for output, and a controller which alternately switches each of the paired data packet memories between a data loading mode ...


4
Julian C Gradinariu: Input buffer with stabilized trip points. Cypress Semiconductor, Christopher P Maiorana, Maiorana & Acosta P C, February 16, 1999: US05872464 (71 worldwide citation)

The present invention provides a circuit and method using a floating PMOS transistor connected in series between the transistors of an input invertor. The floating PMOS transistor may be used to control the amount of current through the transistors. The gate of the floating PMOS transistor may be co ...


5
Jeffrey Watt: Fast turn-on silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection. Cypress Semiconductor, Maiorana & Acosta P C, October 20, 1998: US05825600 (63 worldwide citation)

An apparatus for protecting an integrated circuit against damage from electrostatic discharge (ESD) includes an ESD bus that is connected to multiple input pads through a respective diode. The ESD bus--the node to be protected--is coupled to the negative power supply bus (V.sub.ss) by a FET-triggere ...


6
Nathan Y Moyal: Voltage controlled oscillator (VCO) frequency gain compensation circuit. Cypress Semiconductor, Maiorana & Acosta P C, April 20, 1999: US05896068 (62 worldwide citation)

A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output signal. The control circuit includes a control ...


7
Roland T Knaack, Brian P Evans: Parity generation and check circuit and method in read data path. Cypress Semiconductor, Christopher P Maiorana, Maiorana & Acosta P C, February 16, 1999: US05872802 (28 worldwide citation)

The present invention provides a circuit and method for generating a parity bit and checking the parity of data words positioned in the read data path of a memory device or buffer. The parity check mode can detect errors. The parity generation mode generates EVEN or ODD parity as an additional bit. ...


8
Eric N Mann: Buffer for memory modules with trace delay compensation. Cypress Semiconductor, Christopher P Maiorana, Maiorana & Acosta P C, February 2, 1999: US05867448 (25 worldwide citation)

A circuit comprising a generation circuit for providing a clock signal. A number of compensation circuits may receive the clock signal and may present essentially simultaneously a compensated clock signal at their outputs. The compensated clock signals are generally presented to a plurality of synch ...


9
Gary W Alleven: Methods, circuits and devices for improving crossover performance and/or monotonicity, and applications of the same in a universal serial bus (USB) low speed output driver. Cypress Semiconductor, Christopher P Maiorana & Acosta P C Maiorana, June 15, 1999: US05912569 (24 worldwide citation)

A circuit comprising a first driver circuit, a second driver circuit and a delay circuit. The first driver circuit may be configured to generate a first output signal and a control signal in response to a first input signal. The delay circuit may be configured to generate a delay signal in response ...


10
David B Rees: Ultra low power pumped n-channel output buffer with self-bootstrap. Cypress Semiconductor, Maiorana & Acosta P C, October 27, 1998: US05828262 (22 worldwide citation)

An ultra-low power pumped n-channel transistor output buffer with self-bootstrapping includes an n-channel pullup transistor as the primary pullup device. A gate-to-source capacitance C.sub.gs of the pullup transistor is used to self-bootstrap the input data signal. A pass n-channel transistor is co ...