Robert E Dean, James L Fink: Wafer holding apparatus and method. AT&T Bell Laboratories, Lucian C Canepa, September 25, 1984: US04473455 (92 worldwide citation)

At least three spring-mounted members disposed around the periphery of an aperture in a wafer-mounting plate are arranged to engage and securely hold edge portions of a semiconductor wafer to be processed. When the spring-mounted members are actuated toward the front side of the plate, a wafer can b ...

Martin Feldman, Alan D White, Donald L White: Method and apparatus for aligning mask and wafer members. Bell Telephone Laboratories Incorporated, Lucian C Canepa, April 27, 1982: US04326805 (83 worldwide citation)

Zone plate patterns (12,20,61,62) formed on spaced-apart mask and wafer members (10,60) are utilized for alignment purposes in the fabrication of integrated circuits. By providing off-axis illumination of the patterns, a significant mask-to-wafer alignment capability is provided in an X-ray lithogra ...

Martin Feldman, Alan David White: Zone plate alignment marks. Bell Telephone Laboratories Incorporated, Lucian C Canepa, July 26, 1977: US04037969 (82 worldwide citation)

Certain classes of patterns, for example so-called zone plates, are utilized as alignment marks in the fabrication of integrated circuits. Such a plate, which functions as a lens, provides a high-brightness image that is relatively insensitive to any degradation of the pattern.

Daniel L Flamm, Dan Maydan, David N Wang: Plasma etching of silicon. Bell Telephone Laboratories Incorporated, Lucian C Canepa, January 12, 1982: US04310380 (74 worldwide citation)

By utilizing a fluorine-containing gaseous compound in a plasma etching process, isotropic etching of monocrystalline silicon (48) and doped or undoped polycrystalline silicon (54) is achieved. The etching processes, which are applicable, for example, to pattern delineation in the processing of semi ...

Dennis Joseph Lynes, Peter Theodore Panousis, Robert Leonard Pritchett: Bipolar read-only-memory unit having self-isolating bit-lines. Bell Telephone Laboratories Incorporated, Lucian C Canepa, July 4, 1978: US04099260 (68 worldwide citation)

A semiconductor read-only-memory (ROM) unit fabricated in large-scale-integrated form utilizing the formation of self-isolating bit-line surface regions of one conductivity type directly in a bulk region of the opposite conductivity type. Channel-stop regions of the same conductivity type as the bul ...

Jacob Sosniak, Burton A Unger: Moisture level determination in sealed packages. Bell Telephone Laboratories Incorporated, Lucian C Canepa, September 23, 1980: US04224565 (66 worldwide citation)

A moisture sensing unit (30, FIG. 1 or 58, FIG. 4) is included within a hermetically sealed package. A localized external portion of the package in close proximity to the unit is cooled while the temperature and the alternating-current capacitance and/or conductance characteristic of the unit are me ...

Leonard W Schaper: Low-inductance power/ground distribution in a package for a semiconductor chip. AT&T Bell Laboratories, Lucian C Canepa, March 18, 1986: US04577214 (60 worldwide citation)

A package for a semiconductor chip includes as an integral part thereof a frame-shaped multilayer ceramic capacitor. The chip is mounted within the capacitor structure. Conductive portions of the capacitor serve as the terminals and plates of the capacitor and as planar power and ground members for ...

Dan Maydan: High capacity etching apparatus and method. Bell Telephone Laboratories Incorporated, Lucian C Canepa, November 3, 1981: US04298443 (58 worldwide citation)

An apparatus for high-throughput sputter etching or reactive sputter etching of wafers comprises a multi-faceted wafer holder centrally disposed within a cylindrical chamber. A source of r-f power is capacitively coupled to the holder and the cylindrical chamber is grounded. By establishing a suitab ...

Conrad J Koeneke, Martin P Lepselter, William T Lynch: Fabrication of schottky-barrier MOS FETs. AT&T Bell Laboratories, Lucian C Canepa, December 4, 1984: US04485550 (54 worldwide citation)

Schottky-barrier MOS and CMOS devices are significantly improved by selectively doping the regions surrounding the Schottky-barrier source and drain contacts. For p-channel devices, acceptor doping is carried out in either a one-step or a two-step ion implantation procedure. For n-channel devices, d ...

Victor Herrero, Leonard W Schaper: Water-scale-integrated assembly. American Telephone and Telegraph Company AT&T Bell Laboratories, Lucian C Canepa, June 23, 1987: US04675717 (53 worldwide citation)

The standard silicon wafer of a conventional wafer-scale-integrated assembly is doped to render it highly conductive. Additionally, a conductive layer is formed on the bottom of the wafer. The bottom-side layer forms an easily accessible ground plane of the assembly. Moreover, this layer and the con ...

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