1
Steven P Young, Kamal Chaudhary, Trevor J Bauer: FPGA repeatable interconnect structure with hierarchical interconnect lines. XILINX, Lois D Cartier, Edel M Young, June 22, 1999: US05914616 (330 worldwide citation)

The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic bl ...


2
Ralph D Wittig, Sundararajarao Mohan, Richard A Carberry: FPGA configurable logic block with multi-purpose logic/memory circuit. Xilinx, Patrick T Bever Hoffman & Harms Bever Esq, Lois D Cartier, November 21, 2000: US06150838 (247 worldwide citation)

A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen p ...


3
Danesh Tavana, Wilson K Yee, Stephen M Trimberger: Integrated circuit with field programmable and application specific logic areas. Xilinx, Edel M Young, Adam H Tachner, Lois D Cartier, October 20, 1998: US05825202 (235 worldwide citation)

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By int ...


4
Steven H Kelem, Gary R Lawman: On-chip logic analysis and method for using the same. Xilinx, Edward S Bever Hoffman & Harms Mao Esq, Lois D Cartier, August 22, 2000: US06107821 (231 worldwide citation)

A programmable logic device (PLD) includes a plurality of logic resources, a plurality of multi-bit configuration memories (MBCMs), and a trigger logic structure. The plurality of MBCMs include multiple memory slices that allow the PLD to switch rapidly between configurations, or contexts. In one em ...


5
Donald J Davis, Toby D Bennett, Jonathan C Harris, Ian D Miller, Stephen G Edwards: System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects. Xilinx, LeRoy D Maunu, Lois D Cartier, May 8, 2001: US06230307 (216 worldwide citation)

A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further cont ...


6
David P Schultz, Lawrence C Hung, F Erich Goetting: Method and structure for configuring FPGAS. Xilinx, Patrick T Bever Esq, Lois D Cartier, Bever Hoffman & Harms, March 20, 2001: US06204687 (193 worldwide citation)

An FPGA configuration circuit including a bus interface for applying a bit stream from either a JTAG interface or an input/output block (IOB) interface onto a bus. The bus interface parses a header word from the bit stream into an address field and an operand field. Several registers are connected t ...


7
Steven P Young: FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines. Xilinx, Edel M Young, Lois D Cartier, August 3, 1999: US05933023 (187 worldwide citation)

A structure in which blocks of random access memory, or RAM, are integrated with FPGA configurable logic blocks. Routing lines which access configurable logic blocks also access address, data, and control lines in the RAM blocks. Thus, the logic blocks of the FPGA can use these routing lines to acce ...


8
Emil S Ochotta, Douglas P Wieland: Routing architecture using a direct connect routing mesh. Xilinx, Adam Crosby Heafey Roach & May Tachner Esq, Lois D Cartier, May 30, 2000: US06069490 (178 worldwide citation)

A direct connect mesh routing structure is provided for interconnecting configurable logic blocks within a programmable logic device. The structure includes multi-bit interconnect busses and a highly regular structure distributed throughout a configurable array enabling high direct interconnect util ...


9
Steven A Guccione: Method of designing FPGAs for dynamically reconfigurable computing. Xilinx, Lois D Cartier, Julie Bever Hoffman & Harms Stephenson Esq, June 20, 2000: US06078736 (156 worldwide citation)

A method of designing FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configu ...


10
Gary R Lawman: Configuring an FPGA using embedded memory. Xilinx, Edward S Bever Hoffman & Harms Mao Esq, Lois D Cartier, April 11, 2000: US06049222 (143 worldwide citation)

An FPGA includes an embedded non-volatile memory coupled to a configuration access port. The configuration access port allows the non-volatile memory to program the configuration memory of the FPGA. On power-on or reset, the non-volatile memory configures a first portion of the FPGA using configurat ...