1
Eb Eshun
Anthony K Stamper, Anil K Chinthakindi, Douglas D Coolbaugh, Timothy J Dalton, Daniel C Edelstein, Ebenezer E Eshun, Jeffrey P Gambino, William J Murphy, Kunal Vaed: Air gap under on-chip passive device. International Business Machines Corporation, Lisa U Jaklitsch, Daryl K Neff, February 16, 2010: US07662722 (10 worldwide citation)

A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked inter ...


2
Eb Eshun
Anil K Chinthakindi, Ebenezer E Eshun: Thin film resistor with current density enhancing layer (CDEL). International Business Machines Corporation, Scully Scott Murphy & Presser P C, Lisa U Jaklitsch, September 18, 2007: US07271700 (6 worldwide citation)

A thin film resistor device and method of manufacture includes a layer of a thin film conductor material and a current density enhancing layer (CDEL). The CDEL is an insulator material adapted to adhere to the thin film conductor material and enables the said thin film resistor to carry higher curre ...


3
Eb Eshun
Daniel C Edelstein, Anil K Chinthakindi, Timothy J Dalton, Ebenezer E Eshun, Jeffrey P Gambino, Sarah L Lane, Anthony K Stamper: Integrated circuit comb capacitor. International Business Machines Corporation, Lisa U Jaklitsch, September 8, 2009: US07585722 (6 worldwide citation)

The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention a ...


4
Eb Eshun
Douglas D Coolbaugh, Timothy J Dalton, Daniel C Edelstein, Ebenezer E Eshun, Jeffrey P Gambino, Kevin S Petrarca, Anthony K Stamper, Richard P Volant: Planar vertical resistor and bond pad resistor. International Business Machines Corporation, Lisa U Jaklitsch, Hoffman Warnick, July 1, 2008: US07394110 (4 worldwide citation)

Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor inc ...


5
Eb Eshun
Ebenezer E Eshun, Ronald J Bolam, Douglas D Coolbaugh, Keith E Downes, Natalie B Feilchenfeld, Zhong Xiang He: Method and structure for creation of a metal insulator metal capacitor. International Business Machines Corporation, Lisa U Jaklitsch, Katherine S Brown, June 1, 2010: US07728372 (3 worldwide citation)

The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protecti ...


6
Eb Eshun
Anil K Chinthakindi, Timothy J Dalton, Ebenezer E Eshun, Jeffrey P Gambino, Anthony K Stamper, Kunal Vaed: Methods of fabricating passive element without planarizing. International Business Machines Corporation, Lisa U Jaklitsch, Hoffman Warnick & D Alessandro, September 23, 2008: US07427550 (3 worldwide citation)

Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active c ...


7
H Bernhard Pogge, Roy Yu: Three-dimensional device fabrication method. International Business Machines Corporation, Lisa U Jaklitsch, April 8, 2008: US07354798 (88 worldwide citation)

A method is described for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers. Wafers (1, 2, 3) are bonded together using bonding layers (26, 36) of thermoplastic material such as polyimide; electrical connections are realized by vi ...


8
Oliver D Patterson, Huilong Zhu: Test structures and method of defect detection using voltage contrast inspection. International Business Machines Corporation, Hoffman Warnick, Lisa U Jaklitsch, November 25, 2008: US07456636 (59 worldwide citation)

Test structures and a method for voltage contrast (VC) inspection are disclosed. In one embodiment, the test structure includes: a gate stack that is grounded by a ground to maintain the gate stack in an off state during VC inspection, which allows NFET defect detection using VC inspection prior to ...


9
Qinghuang Lin, Ratnam Sooriyakumaran: Patternable low dielectric constant materials and their use in ULSI interconnection. International Business Machines Corporation, Scully Scott Murphy & Presser, Lisa U Jaklitsch, May 9, 2006: US07041748 (58 worldwide citation)

The present invention relates to ultra-large scale integrated (ULSI) interconnect structures, and more particularly to patternable low dielectric constant (low-k) materials suitable for use in ULSI interconnect structures. The patternable low-k dielectrics disclosed herein are functionalized polymer ...


10
William C Wille, Daniel C Edelstein, William J Cote, Peter E Biolsi, John Fritche, Allan W Upham: Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material. International Business Machines Corporation, Lisa U Jaklitsch, April 18, 2006: US07030031 (47 worldwide citation)

This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. I ...



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