1
Fred B Schneider, Butler Lampson, Edward Balkovich, David Thiel: Fault tolerant computer system with shadow virtual processor. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Lindsay G McGuinness, January 30, 1996: US05488716 (107 worldwide citation)

A fault-tolerant computer system has primary and backup computers. Primary and backup virtual machines running on the computers are controlled by corresponding virtual machine monitors. The virtual machines execute only user-mode instructions, while all kernel-mode instructions are trapped and handl ...


2
Richard L Sites, Richard T Witek: Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Lindsay G McGuinness, September 26, 1995: US05454091 (87 worldwide citation)

A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/s ...


3
David J Sager, Simon C Steely Jr, David B Fite Jr: Multi instruction register mapper. Digital Equipment Corporation, Lindsay G McGuinness, Denis G Maloney, Arthur W Fisher, May 21, 1996: US05519841 (84 worldwide citation)

A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fie ...


4
Jeffrey A Metzger, Barry A Maskas: Update vs. invalidate policy for a snoopy bus protocol. Digital Equipment Corporation, Lindsay G McGuinness, Denis G Maloney, Arthur W Fisher, September 3, 1996: US05553266 (69 worldwide citation)

The present invention is directed to a computer apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus. The bus is operated according to a SNOOPY protocol. The computer apparatus includes a processor and a cache memory ...


5
H Bruce Butts Jr, James N Leahy, Richard B Gillett Jr: Bus event monitor. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Lindsay G McGuinness, June 20, 1995: US05426741 (59 worldwide citation)

A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmi ...


6
Thomas B Hawkins: Phase detector apparatus. Digital Equipment Corporation, Lindsay G McGuinness, Denis G Maloney, Arthur W Fisher, July 23, 1996: US05539345 (59 worldwide citation)

A fault tolerant computer according to the invention includes a processing unit including a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second, abbreviated system bus to receive read data from sai ...


7
Robert A Ulichney: Void and cluster apparatus and method for generating dither templates. Digital Equipment Corporation, Lindsay G McGuinness, Denis G Maloney, Arthur W Fisher, July 9, 1996: US05535020 (49 worldwide citation)

An apparatus for dithering an input image to produce an output array for representation on an output device is described. The apparatus includes an input device to store input image pixels having a first plurality of chrominance or luminance levels; a dithering system including a dither template inc ...


8
Nitin D Godiwala, Kurt M Thaller, Jeffrey A Metzger, Barry A Maskas: Fault management scheme for a cache memory. Digital Equipment Corporation, Lindsay G McGuinness, Denis G Maloney, Arthur W Fisher, May 13, 1997: US05629950 (38 worldwide citation)

The present invention is directed to a method of managing a cache upon detection of an address TAG parity error, The cache includes a plurality of entries for storage of data, with each entry having a corresponding address TAG entry. The method includes the steps of performing a TAG parity check for ...


9
John J Fennelly, Bryan J Rabbitte, Michael M Heavey: Cash pocket for an automatic teller machine. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Lindsay G McGuinness, October 3, 1995: US05454332 (33 worldwide citation)

A cash pocket for an automatic teller machine (ATM) comprises a housing having a rear wall with a slot for receiving banknotes from the dispensing mechanism of the ATM into the housing, and a base upon which the dispensed banknotes come to lie upon being dispensed into the housing. The housing also ...


10
David B Krakauer, Kaizad Mistry, Steven Butler, Hamid Partovi: Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps. Digital Equipment Corporation, Lindsay G McGuinness, Denis G Maloney, Arthur W Fisher, April 1, 1997: US05617283 (32 worldwide citation)

An ESD protection device is provided which includes a self referencing modulation circuit for controlling its operation. The modulation circuit includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of ...