1
Stan T Barone, Ian R Hepburn, Gary E Fladmoe, Robert D Vavra: Method and apparatus for remotely and centrally controlling a plurality of host processors. Unisys Corporation, LeRoy D Maunu, Charles A Johnson, Mark T Starr, May 24, 1994: US05315711 (317 worldwide citation)

A method is disclosed for controlling a plurality of host processors from either a single remote workstation or a plurality of remote workstations. The user interface and level of control at the remote workstation is identical to that which is available at the host processor operations console. Oper ...


2
Donald J Davis, Toby D Bennett, Jonathan C Harris, Ian D Miller, Stephen G Edwards: System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects. Xilinx, LeRoy D Maunu, Lois D Cartier, May 8, 2001: US06230307 (216 worldwide citation)

A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further cont ...


3
Eric R Keller, Steven A Guccione, Delon Levi: Run-time routing for programmable logic devices. Xilinx, LeRoy D Maunu, Edel M Young, November 26, 2002: US06487709 (211 worldwide citation)

A system and method for configuring routing resources of a programmable logic device are presented in various embodiments. In one embodiment, a first function is provided that automatically generates configuration bits for configuration of routing resources to connect a source to a sink. The input p ...


4
Stephen M Trimberger: Field programmable gate array having programming instructions in the configuration bitstream. Xilinx, Edel M Young, LeRoy D Maunu Esq, April 6, 1999: US05892961 (202 worldwide citation)

A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes th ...


5
Bernard J New: Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice. Xilinx, T Lester Wallace, LeRoy D Maunu, Justin Liu, July 12, 2005: US06917219 (185 worldwide citation)

The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is ...


6
Dennis R Konrad, Ralph E Sipple: Data base backup and recovery system and method. Unisys Corporation, LeRoy D Maunu, Charles A Johnson, Mark T Starr, April 4, 1995: US05404508 (180 worldwide citation)

A system and method for maintaining a backup data base. An initial backup copy of a data base is made and stored separate from an active primary data base. Each time the primary data base is updated, audit information pertaining to the data base update is stored in non-volatile storage. A recovery p ...


7
Stephen M Trimberger: Method and apparatus for multiple context and high reliability operation of programmable logic devices. Xilinx, LeRoy D Maunu, May 1, 2007: US07212448 (141 worldwide citation)

A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the robustness of the design when used i ...


8
Yuezhen Fan, Jason Xu, Stephen Wing Ho Tang, Zhi Min Ling: Correlation of electrical test data with physical defect data. Xilinx, LeRoy D Maunu, September 27, 2005: US06950771 (117 worldwide citation)

Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fa ...


9
Eric R Keller, Cameron D Patterson: Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices. Xilinx, LeRoy D Maunu, April 20, 2004: US06725441 (116 worldwide citation)

A method and apparatus for generating a configuration bitstream for a programmable logic device using logic ports associated with logic cores. Logic ports are associated with respective ones of a plurality of logic cores, and logical connections are made between selected ones of the ports of the log ...


10
Anthony D Williams: Method and apparatus for developing and placing a circuit design. Xilinx, LeRoy D Maunu, Edel M Young, Justin Liu, October 7, 2003: US06631508 (112 worldwide citation)

A method and apparatus for developing placement characteristics of a circuit design in conjunction with developing functional aspects of the circuit. In various embodiments, an application programming interface (API) is programmed in a hardware definition language (HDL). The API provides placement d ...