31
Anthony M Balistreri, Andre J Guillemaud: Dual-port memory has the serial register connected to the storage cells by single-sided bitlines. Texas Instruments Incorporated, Richard B Havill, Leo Heiting, Richard L Donaldson, December 12, 1995: US05475649 (4 worldwide citation)

A dual-port memory includes an array of dynamic storage cells and a serial register having a plurality of static stages. Each stage of the serial register is arranged for receiving a data bit from a selected storage cell of the array. A plurality of bitlines is interposed between the storage cells o ...


32
Samir W Rizk, David Caldwell: Data processing apparatus with algebraic memory operation and entry sequence. Texas Instruments Incorporated, Rene E Grossman, Leo Heiting, Melvin Sharp, September 25, 1984: US04473886 (4 worldwide citation)

A data processing apparatus having a plurality of preprogrammed functional operations and at least one user accessible memory includes a generalized input sequence for combining functional operations with data storage in one of the user accessible memories. In the case where a number of user accessi ...


33
Daniel F McLaughlin, Darryl G Walker: Apparatus and method for an active field plate bias generator. Texas Instruments Incorporated, Rich Donaldson, Leo Heiting, William W Holloway, April 16, 1996: US05508962 (4 worldwide citation)

The plate voltage for a Dynamic Random Access Memory storage cell array is provided by two amplifiers. The first amplifier operates at a relatively low power level and compensates for leakage in the storage cell array, the compensation initiated by a departure of the plate from a nominal value which ...


34
Sergio Maggi: Four clock phase N-channel MOS gate. Texas Instruments Incorporated, Andrew J Dillon, Leo Heiting, Mel Sharp, March 17, 1981: US04256976 (3 worldwide citation)

In an N-channel MOS integrated circuit operating in response to a major-major clock having four phases, .phi.1, .phi.2, .phi.3 and .phi.4, each of which has one, but only one, other phase which does not overlap therewith, an improved gate is disclosed wherein a first one of said phases samples an in ...