1
Seiichi Aritome: Programming method to reduce gate coupling interference for non-volatile memory. Micron Technology, Leffert Jay & Polglaze P A, July 15, 2008: US07400532 (141 worldwide citation)

A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a foll ...


2
Gurtej S Sandhu, Sujit Sharan, Anand Srinivasan: Quasi-remote plasma processing method and apparatus. Micron Technology, Leffert Jay & Polglaze P A, December 31, 2002: US06499425 (130 worldwide citation)

In a plasma processing apparatus, a showerhead is provided that allows for selective ionization of one or more process gasses within the showerhead. The showerhead allows the gasses to react after they exit the showerhead. As a result, a greater volume of materials are. available for deposition on a ...


3
Jin Man Han: Architecture and method for NAND flash memory. Micron Technology, Leffert Jay & Polglaze P A, May 13, 2008: US07372715 (123 worldwide citation)

A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries bet ...


4
Frankie F Roohparvar: Error detection, documentation, and correction in a flash memory device. Micron Technology, Leffert Jay & Polglaze P A, April 10, 2007: US07203874 (119 worldwide citation)

A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memor ...


5
Sergey Anatolievich Gorobets: Non-volatile memory control. Lexar Media, Leffert Jay & Polglaze P A, May 8, 2007: US07215580 (103 worldwide citation)

According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time, wherein the method c ...


6
Frankie F Roohparvar: Leakage compensation during program and read operations. Micron Technology, Leffert Jay & Polglaze P A, April 20, 2010: US07701763 (99 worldwide citation)

Methods of operating a memory and a memory are disclosed, such as an analog non-volatile memory device and process that reduces the effects of charge leakage from data cache capacitors, maintaining stored charge levels as data. In one embodiment, data values are compensated for leakage that is unifo ...


7
Anson Ba Phan, Jerrold Allen Beckmann: Direct secondary device interface by a host. Lexar Media, Leffert Jay & Polglaze P A, May 25, 2010: US07725628 (91 worldwide citation)

A storage system having a storage device in communication with a host and including one or more function devices for communicating with application software modules, in accordance with an embodiment of the present invention. Said application software modules issuing vendor specific commands to acces ...


8
Akira Goda, Seiichi Aritome, Todd Marquart: Programming method for NAND EEPROM. Micron Technology, Leffert Jay & Polglaze P A, November 6, 2007: US07292476 (89 worldwide citation)

A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an progra ...


9
Frankic F Roohparvar: Method and architecture to calibrate read operations in synchronous flash memory. Micron Technology, Leffert Jay & Polglaze P A, September 25, 2007: US07274611 (87 worldwide citation)

Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash memory includes a read sense amplifier, a verification sense amplifier, a switch, and an output buffer. The switch alternates electrical connect ...


10
Arup Bhattacharyya: Scalable integrated logic and non-volatile memory. Micron Technology, Leffert Jay & Polglaze P A, April 24, 2007: US07208793 (85 worldwide citation)

A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. A compatible non-vo ...