1
Tich T Dao, Gary R Burke: Floating point microprocessor with directable two level microinstructions. Fairchild Semiconductor Corporation, Lee Patch, Michael Glenn, William H Murray, May 22, 1990: US04928223 (186 worldwide citation)

A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory ...


2
Michael E Thomas, Jeffrey D Chinn: High performance interconnect system for an integrated circuit. Fairchild Semiconductor Corporation, Lee Patch, Michael Glenn, William H Murray, June 12, 1990: US04933743 (139 worldwide citation)

A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is ...


3
Jeffrey B Davis: Output buffer for reducing switching induced noise. National Semiconductor Corporation, Lee Patch, Daniel H Kane, October 2, 1990: US04961010 (128 worldwide citation)

An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor element with the current path first and second terminal leads coupled in parallel with the current path first and sec ...


4
Michael E Thomas: High temperature interconnect system for an integrated circuit. Fairchild Camera and Instrument Corporation, Lee Patch, William H Murray, April 24, 1990: US04920071 (116 worldwide citation)

A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which rem ...


5
William S Phy: Process of forming a compliant lead frame for array-type semiconductor packages. Fairchild Semiconductor Corporation, Lee Patch, James A LaBarre, June 14, 1988: US04751199 (112 worldwide citation)

A lead frame that is suited for use on array types of integrated circuit packages to provide a high degree of compliance for absorbing mechanical stress induced by thermal changes includes a series of individual terminal elements that are connected in a strip form by means of break tabs disposed bet ...


6
Bangalore J Shanker, Jagdish G Belani: Use of a heat pipe integrated with the IC package for improving thermal performance. National Semiconductor Corporation, Gail W Woodward, Lee Patch, Michael A Glenn, March 27, 1990: US04912548 (111 worldwide citation)

A CERDIP housing is provided with a heat pipe that passes through the closure seal lid whereby the heat pipe terminates within the housing cavity at the hot end thereof. A quantity of working fluid, such as fluorinated octane, is contained within the package cavity. The heat pipe communicates with c ...


7
Thanomsak Sankhagowit: Method for making a pre-testable semiconductor die package. National Semiconductor Corporation, Lee Patch, Gail W Woodward, Mark Aaker, January 31, 1989: US04801561 (95 worldwide citation)

An encapsulated die package (20) is shown in which a semiconductor die is connected in a die-attach aperture of a copper foil tape (11). Die contact pads (31) are bonded to the inner ends (31a) of interconnected finger contacts (13) on the tape. Finger contacts etched in the foil include splayed out ...


8
Patrick A Tucci: Method for incorporating window strobe in a data synchronizer. Lee Patch, Gail W Woodward, Michael Glenn, March 17, 1992: US05097489 (94 worldwide citation)

A method and structure for performing data synchronization by delaying the input data for substantially one-half of the VCO signal period and then comparing the phase of the delayed input data to the VCO signal. The phase difference is filtered and controls the frequency of the VCO signal to align t ...


9
Madhukar B Vora: Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size. National Semiconductor Corporation, Lee Patch, Robert C Colwell, August 16, 1988: US04764480 (85 worldwide citation)

There is disclosed a high performance MOS transistor structure of either the N channel or P channel variety and a high performance bipolar transistor structure. A process is disclosed which can make high performance CMOS and high performance bipolar devices on the same die.


10
Harlan Lawler, William S Phy: Die bonding process. Fairchild Semiconductor Corporation, Lee Patch, William H Murray, September 20, 1988: US04772935 (82 worldwide citation)

A process for bonding silicon die to a package. This process comprises the following steps: (a) providing to the back surface of the die an adhesion layer of material which exhibits superior adhesion to both the silicon die and a subsequently applied barrier layer; (b) providing to the adhesion laye ...