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Nicholas G Samra: Content addressable memory system. Motorola, Lee E Chastain, July 8, 1997: US05646878 (69 worldwide citation)

A CAM system (2) stores a plurality of data sets in a plurality of pairs of CAM cells (4) and RAM cells (6). The portion of a particular data set stored in one of the RAM cells is accessed by inputting a tag to CAM cells that matches the portion of the data set stored in the CAM cell associated with ...


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Bryan P Black, Marvin A Denman: Data processor with branch target address cache and method of operation. Motorola, Lee E Chastain, June 25, 1996: US05530825 (62 worldwide citation)

A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. Each pair also includes an offset tag identifying which one of a plurality of instructions indexed by the fetch address generated the entry. A branch unit (20) generates an execution ad ...


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Danny K Jain, David S Levitan, Paul C Rossbach: Data processor with programmable levels of speculative instruction fetching and method of operation. Motorola, International Business Machines, Lee E Chastain, Michael A Davis, September 3, 1996: US05553255 (53 worldwide citation)

A data processor (12) has a branch prediction unit (28) that predicts conditional branch instructions and a control unit (70) therein that monitors the number of unresolved branch instructions. This control unit selectively allows the data processor to fetch the instructions indicated by the branch ...


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Ying wai Ho, Bradley G Burgess: Data processor with rename buffer and FIFO buffer for in-order instruction completion. Motorola, Lee E Chastain, March 19, 1996: US05500943 (50 worldwide citation)

A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36). The first calculation circuitry generates a first and a second result from supplied operands and received programmed instructions. The rename buffer is coupled to the first calculation circuitry and stores ...


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Mitra Nasserbakht, Patrick W Bosshart: Circuit and method for translating signals between clock domains in a microprocessor. Texas Instruments Incorporated, Lee E Chastain, James C Kesterson, Richard L Donaldson, August 18, 1998: US05796995 (50 worldwide citation)

A microprocessor (5) including a clock domain translation circuit (50a) for communicating a digital signal from a high speed clock domain to a low speed clock domain is disclosed. The disclosed microprocessor (5) includes clock generation circuitry (20) which generates internal and bus clocks at dif ...


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David P Burgess, Marvin Denman, Milton M Hood Jr, Mark A Kearney, Lavanya Kling, Graham R Murphy, Seungyoon Peter Song: Data processor with an execution unit for performing load instructions and method of operation. Motorola, IBM, Lee E Chastain, September 2, 1997: US05664215 (48 worldwide citation)

The disclosed data processor (10) dispatches load/store multiple and load/store string instructions to a load/store unit (28) as a sequence of simple load or store instructions. The sequencer unit (18) assigns an entry of a rename buffer (34) to which the load/store unit writes back the data of each ...


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Jose Alvarez, Hector Sanchez, Gianfranco Gerosa: Charge pump with a programmable pump current and system. Motorola, Lee E Chastain, November 8, 1994: US05362990 (47 worldwide citation)

A charge pump has a reference circuitry (18, 20, 22), a first parallel current path (16), at least one second parallel current path (16), a mirror circuit (46), a sourcing circuitry (60, 62) and a sinking circuitry (50, 54, 66, 68). The first and the at least one second parallel current path sink cu ...


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Hector Sanchez, Jose Alvarez, Gianfranco Gerosa: Phase locked loop with low power feedback path and method of operation. Motorola, Lee E Chastain, June 27, 1995: US05428317 (47 worldwide citation)

A phase locked loop (10) has a first (24) and a second (28) feedback path by which a generated clock signal may be phase and frequency matched to an input reference clock signal. The two feedback paths are delay matched so either one may be used to maintain "PLL lock." However, the first path consum ...


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