1
Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven, LAM Christine S, May 26, 2006: WO/2006/055482 (11 worldwide citation)

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


2
Bill Colin S, Kaza Swaroop, Fang Tzu Ning, Spitzer Stuart: Method of programming, reading and erasing memory-diode in a memory-diode array. Spansion, Bill Colin S, Kaza Swaroop, Fang Tzu Ning, Spitzer Stuart, LAM Christine S, July 6, 2006: WO/2006/071683 (1 worldwide citation)

A memory array (140) includes first and second sets of conductors (142), (144) and a plurality of memory-diodes (130), each connecting in a forward direction a conductor (BL) of the first set (142) with a conductor (WL) of the second set (144). An electrical potential is applied across a selected me ...


3
Hamilton Darlene, Bathul Fatima, Horiike Masato, Gershon Eugen, Vanbuskirk Michael A: Read approach for multi-level virtual ground memory. Spansion, Hamilton Darlene, Bathul Fatima, Horiike Masato, Gershon Eugen, Vanbuskirk Michael A, LAM Christine S, April 6, 2006: WO/2006/036783 (1 worldwide citation)

The present invention pertains to a technique (800) for determining the level of a bit in a dual sided ONO flash memory cell (500) where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels (540,542,544). One or more aspects of the present invention take into ...


4
Bathul Fatima, Hamilton Darlene, Horiike Masato: Multi-level ono flash program algorithm for threshold width control. Spansion, Bathul Fatima, Hamilton Darlene, Horiike Masato, LAM Christine S, July 20, 2006: WO/2006/076145 (1 worldwide citation)

Methods (400) of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages (300) are provided. The present invention employs an interactive program algorithm (400) that programs the bits of the wordline o ...


5
Spitzer Stuart, Krieger Juri H, Gaun David: Systems and methods for adjusting programming thresholds of polymer memory cells. Spansion, Spitzer Stuart, Krieger Juri H, Gaun David, LAM Christine S, March 2, 2006: WO/2006/023337 (1 worldwide citation)

Systems and methodologies are provided for adjusting threshold associated with a polymer memory cell's (215, 640) operation by applying thereupon a regulated electric field and/or voltage pulse width, during a post fabrication stage. Such customization of programming thresholds can typically be obta ...


6
Krieger Juri, Spitzer Stuart: Memory device including barrier layer for improved switching speed and data retention. Spansion, Krieger Juri, Spitzer Stuart, LAM Christine S, August 17, 2006: WO/2006/086248

The present memory device (80) includes a first electrode (82), a passive layer (84) on and in contact with the first electrode (82), the passive layer (84) including copper sulfide, a barrier layer (86) on and in contact with the passive layer (84), an active layer (88) on and in contact with the b ...


7
Mandell Aaron, Vanbuskirk Michael A, Spitzer Stuart, Krieger Juri H: Polymer memory with variable data retention time. Spansion, Mandell Aaron, Vanbuskirk Michael A, Spitzer Stuart, Krieger Juri H, LAM Christine S, March 2, 2006: WO/2006/023338

Systems and methodologies are provided for of enabling a polymer memory cell (102, 200) to exhibit variable retention times for stored data therein. Such setting of retention time can depend upon a programming mode and/or type of material employed in the polymer memory cell (102, 200). Short retenti ...


8
Bill Colin S, Vanbuskirk Michael A: Vertical jfet as used for selective component in a memory array. Spansion, Bill Colin S, Vanbuskirk Michael A, LAM Christine S, March 16, 2006: WO/2006/029280

Systems and methods are disclosed that facilitate providing a selective functionality to a polymer memory cell (602) in a memory array while increasing device density in the memory cell array. A vertical JFET (400, 500, 604, 700, 800, 900) is described to which voltages can be selectively applied to ...


9
Melik Martirosian Ashot, Ramsbey Mark T, Randolph Mark W: Memory device having trapezoidal bitlines and method of fabricating same. Spansion, Melik Martirosian Ashot, Ramsbey Mark T, Randolph Mark W, LAM Christine S, July 20, 2006: WO/2006/076625

A memory device (100) and a method of fabrication are provided. The memory device (100) includes a semiconductor substrate (110) and a charge trapping dielectric stack (116, 118, 120) disposed over the semiconductor substrate (110). A gate electrode (122) is disposed over the charge trapping dielect ...


10
Akaogi Takao, Wadhwa Sameer, Achter Michael, Venkatesh Bhimachar: Sense amplifiers with high voltage swing. Spansion, Akaogi Takao, Wadhwa Sameer, Achter Michael, Venkatesh Bhimachar, LAM Christine S, July 6, 2006: WO/2006/071684

A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifie ...



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