1
Qingsu Wang, Gerald Barnett, R Michael Greig, Yi Cheng: System and method for performing real time data acquisition, process modeling and fault detection of wafer fabrication processes. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, January 12, 1999: US05859964 (179 worldwide citation)

A system and method for detecting faults in wafer fabrication process tools by acquiring real-time process parameter signal data samples used to model the process performed by the process tool. The system includes a computer system including a DAQ device, which acquires the data samples, and a fault ...


2
Robert Dawson, Mark W Michael, Basab Bandyopadhyay, H Jim Fulford Jr, Fred N Hause, William S Brennan: Substantially planar semiconductor topography using dielectrics and chemical mechanical polish. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, December 15, 1998: US05850105 (154 worldwide citation)

A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower r ...


3
Mark I Gardner, Fred N Hause: Ultra short trench transistors and process for making same. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, May 18, 1999: US05905285 (121 worldwide citation)

A field effect transistor comprising a semiconductor substrate having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielec ...


4
Richard W Jarvis: Product wafer yield prediction method employing a unit cell approach. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, June 30, 1998: US05773315 (105 worldwide citation)

A method is presented for determining a predicted yield value for a silicon wafer subjected to a wafer fabrication process. The wafer fabrication process forms multiple integrated circuits (i.e., chips) upon a surface of the wafer. A unit cell region is chosen on the surface of the wafer and within ...


5
Prem P Jain: Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description. C A E Plus, Kevin L Conley Rose & Tayon Daffer, March 28, 2000: US06044211 (103 worldwide citation)

A computer-aided synthesis and verification tool is provided for modeling a digital device at a behavioral level and for synthesizing to a structural level utilizing user-defined attributes. The behavioral level is represented as a Data Dependency Graph (DDG) having a plurality of operations (shown ...


6
James C Ashby III, Roy G Tiemann: Apparatus, system and method for recording and/or retrieving audio information. Chips International, Kevin L Conley Rose & Tayon Daffer, December 22, 1998: US05852803 (98 worldwide citation)

An apparatus, system and method is provided for recording and retrieving voice information into a label attachable to a product. The voice information provides a more readily identifiable indicator of the characteristics or contents of the product than conventional written information or labels atta ...


7
Fred N Hause, Basab Bandyopadhyay, Robert Dawson, H Jim Fulford Jr, Mark W Michael, William S Brennan: Dissolvable dielectric method. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, September 14, 1999: US05953626 (91 worldwide citation)

A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment ...


8
Carl K Wakeland: Computer communication network having a packet processor with an execution unit which is variably configured from a programmable state machine and logic. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, February 16, 1999: US05872919 (75 worldwide citation)

A communication system is provided that includes a mechanism for recognizing various communication protocols. That is, the communication system employs a packet processor which can adapt to sent and receive numerous protocols. The packet processor forms a part of a network adapter card or router ass ...


9
Dirk J Wristers, H Jim Fulford, Dim Lee Kwong: Method of forming high pressure silicon oxynitride gate dielectrics. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, October 7, 1997: US05674788 (75 worldwide citation)

A silicon oxynitride (oxynitride) dielectric layer is presented using a process in which nitrogen is incorporated into the dielectric as it is grown upon a silicon substrate. The oxynitride layer is grown at elevated temperature and pressure in an ambient containing N.sub.2 O and/or NO. A MOS gate d ...


10
H Jim Fulford Jr, Robert Dawson, Fred N Hause, Basab Bandyopadhyay, Mark W Michael, William S Brennan: Method of formation of an air gap within a semiconductor dielectric by solvent desorption. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, June 2, 1998: US05759913 (75 worldwide citation)

A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During de ...