1
Ivor Barber: Semiconductor device assembly with minimized bond finger connections. LSI Logic Corporation, Katz & Cotton, August 13, 1996: US05545923 (166 worldwide citation)

A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed ...


2
Shubha Tuljapurkar, George Brecht: High-performance integrated bit-mapped graphics controller. LSI Logic Corporation, Katz & Cotton, November 5, 1996: US05572655 (133 worldwide citation)

A low-cost high-performance technique for providing bit-mapped graphics display controllers is described whereby video frame buffer memory and video controller functions are integrated together on a single chip, permitting very wide video memory formats without the usual penalties of high pin count, ...


3
Roger Patrick, Frank A Bose: Power control and delivery in plasma processing equipment. LSI Logic Corporation, Katz & Cotton, September 17, 1996: US05556549 (114 worldwide citation)

The present invention relates to a system and method for control and delivery of radio frequency power in plasma process systems. The present invention monitors the power, voltage, current, phase, impedance, harmonic content and direct current bias of the radio frequency energy being delivered to th ...


4
Michael D Rostoker, Mark R Schneider, Edwin Fulcher: Method of assembling ball bump grid array semiconductor packages. LSI Logic Corporation, Katz & Cotton, March 24, 1998: US05729894 (102 worldwide citation)

A ball bump grid array package includes dies on one surface of a printed wiring board (PWB) and an array of ball bumps on the other surface of the PWB. The die is interconnected with the ball bumps by bond wires, traces on the one surface of the PWB, vias through the PWB and traces on the other surf ...


5
Michael D Rostoker: Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions. LSI Logic Corporation, Katz & Cotton, July 2, 1996: US05532934 (86 worldwide citation)

A technique for integrated circuit floorplanning using irregularly shaped dies (e.g., triangular, elongated rectangular, parallelogram-shaped, etc.) is described whereby the layout of the integrated circuit die is accomplished by partitioning (slicing) the die into progressively smaller groups of mo ...


6
Michael D Rostoker, Kurt Raymond Raab, John McCormick: Electronic system using multi-layer tab tape semiconductor device having distinct signal, power and ground planes. LSI Logic Corporation, Katz & Cotton, September 1, 1998: US05801432 (70 worldwide citation)

Electronic systems using separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly of the system. TAB technology is utilized to p ...


7
Michael D Rostoker, Nicholas F Pasch: Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate. LSI Logic Corporation, Katz & Cotton, April 2, 1996: US05504035 (67 worldwide citation)

A process of interconnecting a semiconductor device to a substrate wherein solder balls on the semiconductor device are fused with one side of an embedded noble metal foil within a through hole in an interposer structure. Solder balls on the substrate are fused with the metal foil within the structu ...


8
Stony F Peng: Method and apparatus for testing semiconductor devices at speed. LSI Logic Corporation, Katz & Cotton, June 4, 1996: US05524114 (61 worldwide citation)

A method and apparatus for testing semiconductor devices at device operating speed for both proper combinational and timing logic functions with a standard low speed logic tester. A high speed phase-lock-loop system clock of the semiconductor device is frequency and phase locked to the lower speed l ...


9
Robin H Passow, Gordon W Priebe, Ronald D Isliefson, I Ross Mactaggart, Kevin R LeClair: Method and apparatus for a low power self-timed memory control system. LSI Logic Corporation, Katz & Cotton, January 21, 1997: US05596539 (56 worldwide citation)

A self-timed memory control system including a dummy row and column of memory cells along adjacent edges of a core memory array. Control logic receives an external clock signal and initiates address decoding, and also asserts a sense enable signal for activating the sense amplifiers. A dummy driver ...


10
Michael D Rostoker: Methods of polishing semiconductor substrates. LSI Logic Corporation, Katz & Cotton, May 6, 1997: US05626715 (50 worldwide citation)

Methods of polishing, particularly chem-mech polishing a semiconductor substrate to planarize a layer, to remove excess material from atop a layer, and to strip back a defective layer are disclosed. Aluminum oxide particles having a small, well controlled size, and substantially in the alpha phase p ...



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