1
John Michael Borkenhagen, William Thomas Flynn, Andrew Henry Wottreng: Altering thread priorities in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, April 3, 2001: US06212544 (273 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


2
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Sheldon Bernard Levenstein, Andrew Henry Wottreng: Thread switch control in a multithreaded processor system. International Business Machines Corporation, Karuna Ojanen, May 20, 2003: US06567839 (208 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


3
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Andrew Henry Wottreng: Method and apparatus to force a thread switch in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, June 13, 2000: US06076157 (177 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


4
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Andrew Henry Wottreng: Method and apparatus for selecting thread switch events in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, February 24, 2004: US06697935 (147 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


5
Kenneth J Kiefer, David A Luick, John Christopher Willis: Moving data in and out of processor units using idle register/storage functional units. International Business Machines Corporation, Karuna Ojanen, April 24, 2001: US06223208 (90 worldwide citation)

In a computer system and a processor which has the capability to do multithreaded processor, the computer system and processor use idle register/storage functional units within the processor core to transfer the state of a thread out of the processor to memory or from memory to the processor core. T ...


6
David D Andaleon, Leonard M Napolitano Jr, G Robert Redinbo, William O Shreeve: Fault-tolerant corrector/detector chip for high-speed data processing. The United States of America represented by the United States Department of Energy, Karuna Ojanen, James H Chafin, William R Moser, March 1, 1994: US05291496 (79 worldwide citation)

An internally fault-tolerant data error detection and correction integrated circuit device (10) and a method of operating same. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum is provided wi ...


7
Hideto Niijima, Takashi Toyooka: Nonvolatile memory with flash erase capability. International Business Machines Corporation, Matthew J Bussan, Karuna Ojanen, March 31, 1998: US05734816 (75 worldwide citation)

A nonvolatile memory with flash erase capability includes a plurality of clusters each having a plurality of sectors, each of the sectors holding the attribute information for identification. A cluster information sector is placed at the top of a cluster to which it belongs. A data sector is placed ...


8
George Wayne Nation, Robert N Newshutz, John Christopher Willis: Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers. International Business Machines Corporation, Karuna Ojanen, May 15, 2001: US06233599 (75 worldwide citation)

An apparatus and method for performing multithreaded operations includes partitioning the general purpose and/or floating point processor registers into register subsets, including overlapping register subsets, allocating the register subsets to the threads, and managing the register subsets during ...


9
Richard James Eickemeyer: Selective flush of shared and other pipeline stages in a multithread processor. International Business Machines Corporation, Karuna Ojanen, February 17, 2004: US06694425 (74 worldwide citation)

In a simultaneous multithread processor, a flush mechanism of a shared pipeline stage is disclosed. In the preferred embodiment, the shared pipeline stage happens to be one or all of the fetch stage, the decode stage, and/or the dispatch stage and the flush mechanism flushes instructions at the disp ...


10
Salvatore N Storino, Gregory J Uhlmann: Changing the thread capacity of a multithreaded computer processor. International Business Machines Corporation, Karuna Ojanen, June 8, 2004: US06748556 (71 worldwide citation)

In a multithreaded processor, a method and an apparatus to selectively disable one or more threads is disclosed. As multithreading is increasingly becoming the normative paradigm of computer architecture, there still may instances which warrant disabling a thread, such as using operating systems not ...