1
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Charles W Koburger III: Accessible chip stack and process of manufacturing thereof. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph Petrokaitis Esq, May 5, 2009: US07528494 (174 worldwide citation)

A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip de ...


2
Zhijiong Luo, Young Way Teh, Atul C Ajmera: Methods of forming semiconductor devices using embedded L-shape spacers. International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ohlandt Greeley Ruggiero & Perle L, Joseph Petrokaitis Esq, IBM Corporation, July 20, 2010: US07759206 (85 worldwide citation)

A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the substrate a p ...


3
Thomas W Dyer: Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure. International Business Machines Corporation, Gibb I P Law Firm, Joseph Petrokaitis Esq, June 21, 2011: US07964910 (9 worldwide citation)

Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, hav ...


4
Hoki Kim, Geng Wang: Floating body control in SOI DRAM. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph Petrokaitis Esq, October 21, 2008: US07440353 (8 worldwide citation)

A system and method wherein a DRAM memory device on an integrated circuit (IC) uses a control logic device to initiate a body refresh operation for maintaining a low voltage at a floating body and discourage data loss. A plurality of DRAM cells are connected to a first word line circuit and a first ...


5
David L Edwards, Sushumna Iruvanti, Hilton T Toy, Wei Zou: Thermal paste containment for semiconductor modules. International Business Machines Corporation, Gibb & Rahman, Joseph Petrokaitis Esq, September 11, 2007: US07268428 (7 worldwide citation)

A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of ...


6
Kangguo Cheng: CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph Petrokaitis Esq, October 29, 2013: US08569159 (6 worldwide citation)

A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation dif ...


7
Chih Chao Yang, Daniel C Edelstein, Theodorus E Standaert: Via gouged interconnect structure and method of fabricating same. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph Petrokaitis Esq, June 21, 2011: US07964966 (5 worldwide citation)

An interconnect structure including a gouging feature at the bottom of a via opening and a method of forming the same are provided. The method of the present invention does not disrupt the coverage of the deposited trench diffusion barrier in a line opening that is located atop the via opening, and/ ...


8
Bruce K Furman, Kenneth C Marston, Jiantao Zheng, Jeffrey A Zitz: Electronic package method and structure with cure-melt hierarchy. International Business Machines Corporation, Gibb I P Law Firm, Joseph Petrokaitis Esq, November 16, 2010: US07834442 (4 worldwide citation)

Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip ...


9
Louis L Hsu, Xu Ouyang, Chih Chao Yang: Modularized three-dimensional capacitor array. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph Petrokaitis Esq, May 29, 2012: US08188786 (4 worldwide citation)

A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capaci ...


10
Charles L Arvin, Hai P Longworth, David J Russell, Krystyna W Semkow: Bump pad metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph Petrokaitis Esq, July 31, 2012: US08232655 (4 worldwide citation)

An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu por ...