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Katherina Babich
Deok kee Kim, Kenneth T Settlemyer Jr, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P Mahorowala, Harald Okorn Schmidt: Methods and structures for protecting one area while processing another area on a chip. International Business Machines Corporation, Whitman Curtis Christofferson & Cook PC, Joseph P Abate, March 3, 2009: US07497959 (4 worldwide citation)

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided whi ...


2
Cyprian Emeka Uzoh, James McKell Edwin Harper: Method of electrochemical mechanical planarization. International Business Machines Corporation, Joseph P Abate, September 15, 1998: US05807165 (250 worldwide citation)

A method of planarizing a layer of a workpiece such as a semiconductor wafer includes rotating the layer against an electrolytic polishing slurry and flowing an electrical current through the slurry and through only one major side and/or minor sides of the layer, to remove portions of the layer. The ...


3
Fariborz Assaderaghi, Louis Lu Chen Hsu, Jack A Mandelman: Mixed memory integration with NVRAM, dram and sram cell structures on same substrate. International Business Machines Corporation, Joseph P Abate, July 23, 2002: US06424011 (194 worldwide citation)

A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same semiconductor on insulator substrate. An NVRAM cell structure. Processes for forming a mem ...


4
Cyprian Emeka Uzoh, Stephen Edward Greco: Method to selectively fill recesses with conductive metal. International Business Machines Corporation, Joseph P Abate, Pollock Vande Sande & Amernick, October 31, 2000: US06140234 (188 worldwide citation)

Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and pattern ...


5
Cyprian Emeka Uzoh, James McKell Edwin Harper: Apparatus for electrochemical mechanical planarization. International Business Machines Corporation, Joseph P Abate, June 15, 1999: US05911619 (158 worldwide citation)

A method of planarizing a layer of a workpiece such as a semiconductor wafer includes rotating the layer against an electrolytic polishing slurry and flowing an electrical current through the slurry and through only one major side and/or minor sides of the layer, to remove portions of the layer. The ...


6
Fariborz Assaderaghi, Bijan Davari, Louis L Hsu, Jack A Mandelman, Ghavam G Shahidi: Two-device memory cell on SOI for merged logic and memory applications. International Business Machines Corporation, Joseph P Abate, Whitham Curtis & Whitham, July 21, 1998: US05784311 (152 worldwide citation)

A two-MOSFET device memory cell, based on conventional SOI complementary metal oxide technology, in which charge is stored on the body of a first MOSFET, with a second MOSFET connected to the body for controlling the charge in accordance with an information bit. Depending on the stored charge, the b ...


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Richard Bealkowski, Ralph Murray Begun, Louis Bennie Capps Jr: Method and apparatus for providing updated firmware in a data processing system. International Business Machine, Jeffrey L LaBau, Bruce D Johse, Joseph P Abate, March 2, 1999: US05878256 (136 worldwide citation)

A programmable firmware store for a personal computer system includes a plurality of nonvolatile alterable electronic memories connected in a mutually paralleled circuit arrangement. The memories are connected to a controller that controls the memories to read firmware from and write firmware into t ...


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Effendi Leobandung, Devendra K Sadana, Dominic J Schepis, Ghavam G Shahidi: Process of making densely patterned silicon-on-insulator (SOI) region on a wafer. International Business Machines Corporation, Joseph P Abate Esq, Ratner & Prestia, April 10, 2001: US06214694 (132 worldwide citation)

A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide ...


9
Louis L Hsu, Jack A Mandelman, Chih Chun Hu: Field effect transistor having a floating gate. International Business Machines Corporation, Joseph P Abate, Connolly Bove Lodge & Hutz, June 12, 2001: US06245613 (126 worldwide citation)

A field effect transistor which comprises a semiconductor substrate having a source region and a drain region separated by a channel region; a conductive floating gate formed over a first portion of the channel region adjacent to the doped source region and recessed into the semiconductor substrate; ...


10
Bruce B Doris, Diane C Boyd, Meikei Leong, Thomas S Kanarsky, Jakub T Kedzierski, Min Yang: Hybrid planar and FinFET CMOS devices. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph P Abate Esq, July 31, 2007: US07250658 (126 worldwide citation)

The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an sili ...



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