1
Gun Ho Song, Si Chan Sung: Method of producing lead frame having uneven surfaces. Samsung Electronics, Jones Volentine L, March 6, 2001: US06197615 (228 worldwide citation)

A lead frame for manufacturing semiconductor device packages has inner leads, tie bars and a die pad that are formed with irregular dimples on their respective upper and lower surfaces. This improves the bonding strength between the lead frame and the molding compound as well as between the die pad ...


2
Do Soo Jeong, Kyung Seob Kim: Semiconductor device package having twice-bent tie bar and small die pad. Samsung Electronics, Jones Volentine L L C, May 8, 2001: US06229205 (172 worldwide citation)

A semiconductor device package includes a die pad to which a semiconductor chip is vertically attached, having a smaller horizontal size than a horizontal size of the semiconductor chip. The package includes a plurality of inner leads which are electrically connected to the semiconductor chip, a plu ...


3
Sung Min Sim: Method of manufacturing semiconductor chip package. Samsung Electronics, Jones & Volentine L, May 19, 1998: US05753532 (171 worldwide citation)

A method for manufacturing semiconductor chip package comprising steps of: (a) preparing a lead frame which comprises a pair of opposing side rails which have a plurality of through holes on their upper surface; a die pad onto which a chip will be mounted; a pair of rows of leads, each row being dis ...


4
Jyoti Kiron Bhardwaj, Huma Ashraf, Babak Khamsehpour, Janet Hopkins, Alan Michael Hynes, Martin Edward Ryan, David Mark Haynes: Method of surface treatment of semiconductor substrates. Surface Technology Systems, Jones & Volentine L, April 18, 2000: US06051503 (168 worldwide citation)

This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more ...


5
Do Soo Jeong, Min Cheol An, Seung Ho Ahn, Hyeon Jo Jeong, Ki Won Choi: Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements. Samsung Electronics, Jones & Volentine L, April 28, 1998: US05744827 (155 worldwide citation)

A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps. The three dimensional package device includes a plurality of individual semiconductor devices, e ...


6
Tai Su Park, Han Sin Lee, Yu Gyun Shin: Method for forming a trench isolation structure in an integrated circuit. Samsung Electronics, Jones Volentine L, August 22, 2000: US06107143 (149 worldwide citation)

A method is provided for forming a trench isolation structure in an integrated circuit that has a better reliability and an acceptable time-dependent dielectric breakdown over a greater range of production. The manufacturing method involves etching a trench in a semiconductor substrate, forming a si ...


7
Hiroyuki Noto: Tag with IC capacitively coupled to antenna. Oki Electric Indusry, Jones & Volentine L, December 29, 1998: US05854480 (136 worldwide citation)

A tag has an integrated circuit (IC), electrode plates included in the IC, an electrically insulating film covering the electrode plates, antenna terminals each facing one of the electrode plates with the insulating film sandwiched between, antennas each being connected to one of the antenna termina ...


8
Jueng gil Lee, Jung ho Lee, Hyo rak Nam: Method for manufacturing a liquid crystal display. Samsung Electronics, Jones Volentine L, December 28, 1999: US06008065 (116 worldwide citation)

A method for manufacturing a liquid crystal display is provided. The method includes the steps of forming a gate electrode and a gate pad by sequentially depositing a first metal film and a second metal film on a substrate of a TFT area and a pad area, respectively, by a first photolithography proce ...


9
Shinji Ohuchi: Using grooves as alignment marks when dicing an encapsulated semiconductor wafer. Oki Electric, Jones Volentine L, August 22, 2000: US06107164 (113 worldwide citation)

Described herein is a method of manufacturing a semiconductor device according to the invention of the present application. According to the method, protruded electrodes are formed on a plurality of chip areas of a wafer having the plurality of chip areas on the surface thereof. Grooves are defined ...


10
Hwan Ho Seong: Power factor correction circuit and circuit therefor having sense-FET and boost converter control circuit. Samsung Electronics, Jones & Volentine L, May 26, 1998: US05757635 (103 worldwide citation)

A power factor correction circuit includes a boost converter, a zero-current detector for detecting a period in which an inductor current is zero, a half-wave rectifier for supplying a power voltage proportional to an output voltage of the boost converter, a control voltage generator for generating ...