1
Luther W Ricketts, Paul M Dormans: Premium interactive communication system. The Magnavox Company, Joe E Barbee, Thomas A Briody, William J Streeter, December 14, 1976: US03997718 (180 worldwide citation)

A cable television and communication system is disclosed which is suitable for community antenna television (CATV) closed circuit television (CCTV) and other types of signal distribution systems with service function applications such as for use in hotel, motel, apartment complexes, and the like. Th ...


2
Hugh W Littlebury, Marion I Simmons: Apparatus and method for burning in integrated circuit wafers. Motorola, Joe E Barbee, Stuart T Langley, November 6, 1990: US04968931 (154 worldwide citation)

A method of burning in integrated circuits on a semiconductor wafer is provided, wherein a burn-in chamber having a flexible membrane probe which is sized so that it can couple to a plurality of contact pads on the semiconductor wafer at one time. The semiconductor wafer is heated to a predetermined ...


3
Francine Y Robb, Stephen P Robb: Fabricating dual gate thin film transistors. Motorola, Joe E Barbee, Rennie William Dover, November 30, 1993: US05266515 (153 worldwide citation)

A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film tra ...


4
Yefim Bukhman: Distributed polishing head. Motorola, Joe E Barbee, July 27, 1993: US05230184 (151 worldwide citation)

A distributed polishing head assembly (17) has a flexible membrane (14), and a plurality of periodic polishing pads (12) that are attached to the flexible membrane (14). The polishing pads (12) are made from a flat semiconductor wafer that has been sawed into small pieces. The polishing head is rubb ...


5
William Chapman, Gwo Jer Chang, DiAnn Fox, Shoarong Zhu: Process flow information management system. Motorola, Michael A Waters, Joe E Barbee, June 14, 1994: US05321605 (145 worldwide citation)

A memory structure and related method for collecting and maintaining data descriptive of a multiplicity of interrelated process flows is disclosed. A complex memory structure includes job entities, operation entities, and process entities. Operation entities are subordinate to job entities, and proc ...


6
Hugh W Littlebury, Marion I Simmons: Low resistance probe for semiconductor. Motorola, Joe E Barbee, January 5, 1993: US05177438 (142 worldwide citation)

A probe (10) that can be used for forming a low resistance electrical connection to a semiconductor die includes a contact (18) that is created on a compliant layer (12) which is supported by a substrate (11). Pressure applied to the contact (18) compresses the compliant layer (11) which causes a di ...


7
Hugh W Littlebury: Method for parallel testing of semiconductor devices. Motorola, Joe E Barbee, Stuart T Langley, April 30, 1991: US05012187 (133 worldwide citation)

A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines ...


8
William Chapman, William Capen, Gwo Jer Chang, Christopher Handorf, Anant Raman, Ajay Sevak, Kolur Venkatesh: Method of planning organizational activities. Motorola, Joe E Barbee, October 19, 1993: US05255181 (128 worldwide citation)

A method for translating complex process flow networks into plans or schedules for the manufacturing of products or the performance of other organizational activities is disclosed. The method maintains a time-valued list of existing commitments to resources. Allocations of these resources are made t ...


9
Donald J Voss: Video graphic dynamic RAM. Motorola, Joe E Barbee, February 24, 1987: US04646270 (127 worldwide citation)

A memory chip containing a standard dynamic RAM having the capability to serially read out data at a high rate of speed while performing standard RAM operations is provided. A standard memory latches a complete row of data into a latch. The data from the latch is then transferred upon command to a s ...


10
David N Okada: High voltage transistor having reduced on-resistance. Motorola, Gary W Hoshizaki, Joe E Barbee, March 15, 1994: US05294824 (113 worldwide citation)

A method for forming a plurality of surface conduction paths (33) in a conductive region (16) of a first conductivity type. A plurality of areas (17) of a second conductivity type are formed in the conductive region (16). The plurality of areas (17) deplete the conductive region (16) when a reverse ...