1
George R Leal, Jie Hua Zhao, Edward R Prack, Robert J Wenzel, Brian D Sawyer, David G Wontor, Marc Alan Mangrum: Circuit device with at least partial packaging, exposed active surface and a voltage reference plane. Freescale Semiconductor, Susan C Hill, Joanna G Chiu, July 26, 2005: US06921975 (150 worldwide citation)

A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as ...


2
Owen R Fay, Craig S Amrine, Kevin R Lish: Die encapsulation using a porous carrier. Freescale Semiconuctor, David G Dolezal, Joanna G Chiu, March 21, 2006: US07015075 (130 worldwide citation)

A process for encapsulating an integrated circuit die (403) using a porous carrier (101). In one example, an adhesive structure (e.g. tape) is applied to a porous carrier. Integrated circuit die is then placed on the adhesive structure. The integrated circuit die is then encapsulated to form an enca ...


3
James K Schaeffer, Darrell Roan, Dina H Triyoso, Olubunmi O Adetutu: Method for treating a semiconductor surface to form a metal-containing layer. Freescale Semiconductor, Joanna G Chiu, Robert L King, November 7, 2006: US07132360 (101 worldwide citation)

A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely ...


4
Qing Tan, Stanley Craig Beddingfield, Douglas G Mitchell: Fine pitch bumping with improved device standoff and bump volume. Motorola, Joanna G Chiu, April 16, 2002: US06372622 (86 worldwide citation)

Embodiments of the present invention relate generally to solder bump formation and semiconductor device assemblies. One embodiment related to a method for forming a bump structure includes providing a semiconductor device (


5
Robert E Jones, Bruce E White: Semiconductor device and method therefor. Motorola, James L Clingan Jr, Joanna G Chiu, June 10, 2003: US06576532 (75 worldwide citation)

A heteroepitaxial structure is made using nanocrystals that are formed closer together than normal lithography patterning would allow. The nanocrystals are oxidized and thus selectively etchable with respect to the substrate and surrounding material. In one case the oxidized nanocrystals are removed ...


6

7

8
Gowrishankar L Chindalore, Paul A Ingersoll, Craig T Swift, Alexander B Hoefler: Non-volatile memory device and method for forming. Freescale Semiconductor, Joanna G Chiu, Daniel D Hill, May 3, 2005: US06887758 (46 worldwide citation)

A semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into the semiconductor substrate (20). An oxide-nitride-oxide structure (36, 38, 40) is formed over the semiconductor substrate (20). A halo region (46) having the first conductivity type i ...


9
George R Leal, Jie Hua Zhao, Edward R Prack, Robert J Wenzel, Brian D Sawyer, David G Wontor, Marc Alan Mangrum: Circuit device with at least partial packaging and method for forming. Freescale Semiconductor, Susan C Hill, Joanna G Chiu, April 22, 2008: US07361987 (45 worldwide citation)

A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as ...


10
Robert J Wenzel, Peter R Harper: Semiconductor package having optimized wire bond positioning. Freescale Semiconductor, Joanna G Chiu, Robert L King, November 2, 2004: US06812580 (45 worldwide citation)

Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least ...