1
Howard F Lee, Benjamin F Cutler: Method and apparatus for automatically archiving a file system. Jeffrey Van Myers, December 26, 2006: US07155465 (228 worldwide citation)

In a digital data processing system having an on-line file system component, a method and apparatus for archiving the contents of a selected client volume stored on the file system. The archiving is performed automatically, beginning with an initial duplication of the existing contents of the client ...


2
Hunter L Scales III, William C Moyer, William D Wilson: Bus master having burst transfer mode. Motorola, Jeffrey Van Myers, January 17, 1989: US04799199 (190 worldwide citation)

A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to ...


3
Louis C Parrillo, Stephen S Poon: LDD CMOS process. Motorola, John A Fisher, Jeffrey Van Myers, June 28, 1988: US04753898 (179 worldwide citation)

A process is disclosed for fabricating LDD CMOS structures having a reduced mask count and improved manufacturability. In one embodiment of the invention a CMOS structure is formed having gate insulators overlying N and P type surface regions. Gate electrodes are formed on each of the surface region ...


4
Donald L Tietjen: Wait mode power reduction system and method for data processor. Motorola, John A Fisher, Jeffrey Van Myers, Jonathan P Meyer, October 25, 1988: US04780843 (155 worldwide citation)

A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal i ...


5
Clinton Kuo: Intelligent write in an EEPROM with data and erase check. Motorola, John A Fisher, Jeffrey Van Myers, James L Clingan Jr, August 9, 1988: US04763305 (151 worldwide citation)

A memory provides a byte program mode which avoids unnecessary erase and program cycles. If a byte is to be programmed, the new data to be written is first compared to the existing data in the byte. If the old data is the same as the new data, there is no need to do a conventional erase/program cycl ...


6
Michael B McShane: Low cost integrated circuit bonding process. Motorola, John A Fisher, Jeffrey Van Myers, David L Mossman, April 28, 1987: US04661192 (122 worldwide citation)

A low cost process for bonding a plurality of integrated circuit die to a variety of die support frames using existing, readily available equipment. Tape automatic bonding (TAB) processes offer a number of new possibilities in the assembly and packaging of integrated circuits. However, the investiga ...


7
James J Remedi: Method for reducing power consumed by a static microprocessor. Motorola, John A Fisher, Jeffrey Van Myers, July 19, 1988: US04758945 (105 worldwide citation)

In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instructi ...


8
James R Pfiester: Method for fabricating MOS transistors having gates with different work functions. Motorola, John A Fisher, Jeffrey Van Myers, David L Mossman, May 17, 1988: US04745079 (94 worldwide citation)

A method for fabricating an insulated gate field effect transistor (IGFET) having a semiconductor gate with a first portion and a second portion where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon gate of a first conductiv ...


9
Kevin L Kloker, Ronald H Cieslak: X.times.Y Bit array multiplier/accumulator circuit. Motorola, Anthony J Sarli Jr, Jeffrey Van Myers, Robert L King, March 11, 1986: US04575812 (94 worldwide citation)

An X.times.Y bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and sy ...


10
John E Zolnowsky, Charles L Whittington, William M Keshlear: Memory management unit. Motorola, Anthony J Sarli Jr, Jeffrey Van Myers, September 25, 1984: US04473878 (93 worldwide citation)

A memory management unit of use in a memory management system. The memory management unit selectively maps a logical address to a respective physical address in accordance with a selected one of a plurality of segment descriptors, each of which defines a logical-to-physical address mapping and a ran ...