1
Samson Huang: Multiple clock frequency divider with fifty percent duty cycle output. Intel Corporation, Jeffery S Draeger, June 22, 1999: US05914996 (111 worldwide citation)

A clock divider circuit and a system using the same. The clock divider circuit has a clock input coupled to receive an input clock signal having an input clock frequency. Clock division logic generates an output clock signal having a fifty percent duty cycle and an output clock frequency which is an ...


2
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Enhanced highly pipelined bus architecture. Intel Corporation, Jeffery S Draeger, June 14, 2005: US06907487 (11 worldwide citation)

A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to dr ...


3
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Snoop phase in a highly pipelined bus architecture. Intel Corporation, Jeffery S Draeger, April 12, 2005: US06880031 (8 worldwide citation)

A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controll ...