1
Travis A Bogard: Instant messaging via telephone interfaces. Tellme Networks, Jeanette S Harms, Bever Hoffman & Harms, June 29, 2004: US06757365 (450 worldwide citation)

A method and apparatus for enabling users of a phone based speech activated system such as a voice portal to communicate with users of an Internet based instant messenger (IM) service is described. Phone based users are able to send and receive IMs. Incoming messages can cause an asynchronous notifi ...


2
Stephen M Trimberger, Richard A Carberry, Robert Anders Johnson, Jennifer Wong: Time multiplexed programmable logic device. Xilinx, Jeanette S Harms, Norman R Klivans, July 8, 1997: US05646545 (341 worldwide citation)

A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a ...


3
Tsu Jae King, Victor Moroz: Segmented channel MOS transistor. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, July 24, 2007: US07247887 (324 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


4
Stephen M Trimberger, Richard A Carberry, Robert Anders Johnson, Jennifer Wong: Method of time multiplexing a programmable logic device. Xilinx, Jeanette S Harms, November 12, 2002: US06480954 (255 worldwide citation)

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the inter ...


5
Stephen M Trimberger: PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays. Xilinx, Adam H Tachner, Jeanette S Harms, July 4, 2000: US06084429 (253 worldwide citation)

A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks ...


6
Tsu Jae King, Victor Moroz: Integrated circuit on corrugated substrate. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, March 13, 2007: US07190050 (245 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


7
Khue Duong: Tile-based modular routing resources for high density programmable logic device. Xilinx, Anthony C Wagner Murabito & Hao Murabito, Jeanette S Harms, March 9, 1999: US05880598 (231 worldwide citation)

Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are p ...


8
Stephen M Trimberger: Optimizing and operating a time multiplexed programmable logic device. Xilinx, Jeanette S Harms, Norman R Klivans, June 2, 1998: US05761483 (227 worldwide citation)

A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the physical resources include configurable logic elements), determining an appropriate micro cycle for each conf ...


9
Bernard J New, Robert Anders Johnson, Ralph Wittig, Sundararajarao Mohan: Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM. Xilinx, E Eric Hoffman, Jeanette S Harms, July 18, 2000: US06091263 (227 worldwide citation)

A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store ...


10
Tsu Jae King, Victor Moroz: Integrated circuit on corrugated substrate. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, May 5, 2009: US07528465 (226 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...