1
Scot A Kellar, Sarah E Kim, R Scott List: Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same. Intel Corporation, Jay P Beale, May 3, 2005: US06887769 (190 worldwide citation)

A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated ...


2
Scot A Kellar, Sarah E Kim, R Scott List: Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration. Intel Corporation, Jay P Beale, May 2, 2006: US07037804 (165 worldwide citation)

A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at desi ...


3
Michael D Goodner, Jihperng Leu: Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide. Intel Corporation, Jay P Beale, August 2, 2005: US06924222 (17 worldwide citation)

An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed adjacent a sacrificial dielectric layer. Subsequent to other processing treatments, a portion of the s ...


4
John F Magana, M Lawrence A Dass: Wafer level electro-optical sort testing and wafer level assembly of micro liquid crystal-on silicon (LCOS) devices. Intel Corporation, Jay P Beale, May 10, 2005: US06891592 (13 worldwide citation)

A method of manufacturing liquid crystal devices on a silicon substrate is disclosed. Such a method is accomplished by preparing a silicon substrate having a plurality of die arranged in an array with scribe streets between the dies, and alignment marks within designated scribe streets; preparing a ...


5
Nagesh K Vodrahalli, Jaiom S Sambyal, Biswajit Sur: Compact optical package with modular optical connector. Intel Corporation, Jay P Beale, March 1, 2005: US06860642 (11 worldwide citation)

An optical connector comprises an optical circuit and a package casing. The package casing has an integrated modular optical connector, which has multiple optical waveguides.


6
Tom E Pearson, George Arrigotti, Christopher D Combs, Raiyomand F Aspandiar: Extension mechanism and method for assembling overhanging components. Intel Corporation, Jay P Beale, October 5, 2004: US06801436 (3 worldwide citation)

A mechanism and method are provided for assembling a printed circuit board having a first surface, a second surface and an edge. The printed circuit board may include at least one female member to receive a corresponding male member. The mechanism may include an extension board having an edge to cou ...


7
Valery M Dubin, Vincent R Caillouette, Christopher D Thomas, Chin Chang Cheng: Apparatus and method for electroless spray deposition. Intel Corporation, Jay P Beale, January 18, 2005: US06843852 (2 worldwide citation)

An apparatus for electroless spray deposition of a metal layer on a substrate, e.g., a Co shunt or barrier layer on a Cu layer on a semiconductor wafer, includes a processing chamber to hold the substrate, the processing chamber including at least one section movable between an open position to allo ...


8
Tom E Pearson, George Arrigotti, Christopher D Combs, Raiyomand F Aspandiar: Extension mechanism and method for assembling overhanging components. Intel Corporation, Jay P Beale, July 12, 2005: US06917524 (1 worldwide citation)

A mechanism and method are provided for assembling a printed circuit board having a first surface, a second surface and an edge. The printed circuit board may include at least one female member to receive a corresponding male member. The mechanism may include an extension board having an edge to cou ...


9
Peter G Tolchinsky, Irwin Yablok, Mohamad A Shaheen: Method of forming silicon on insulator wafers. Intel Corporation, Jay P Beale, June 28, 2005: US06911380 (1 worldwide citation)

A method is provided for fabricating an SOI water. This may involve forming a silicon substrate and implanting oxygen into the substrate. Damaged portions of the implanted silicon may be healed/cured by CMP or anneal, for example. An epi layer may then be deposited over the healed/cured regions of t ...


10
Brian D Possley: Gate array architecture. Intel Corporation, Jay P Beale, June 22, 2004: US06753209 (1 worldwide citation)

Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially ove ...