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Sudhir K Madan: Low voltage, low power static random access memory cell. Texas Instruments Incorporated, Jacqueline J Garner, Wade James Brady, Richard L Donaldson, July 18, 2000: US06091626 (50 worldwide citation)

A ten transistor low voltage, low power static random access memory cell (10) includes a first inverter (12) cross-coupled to a second inverter (18). A series combination of a first pass transistor (24) and a first bitline select transistor (28) is connected between an output node (13) of the first ...


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Francis G Celii, Scott R Summerfelt, Mahesh Thakre: FeRAM capacitor stack etch. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Frederick J Telecky Jr, April 18, 2006: US07029925 (49 worldwide citation)

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with r ...


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Luigi Colombo, Manuel Quevedo Lopez, James J Chambers, Mark R Visokay, Antonio L P Rotondaro: High-k gate dielectric with uniform nitrogen profile and methods for making the same. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Frederick J Telecky Jr, October 26, 2004: US06809370 (49 worldwide citation)

High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.


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Habib N Najm, Mehrdad M Moslehi, Somnath Banerjee, Lino A Velo: Apparatus and method for determining wafer temperature using pyrometry. Texas Instruments Incorporated, Jacqueline J Garner, William E Hiller, Richard L Donaldson, April 19, 1994: US05305417 (47 worldwide citation)

In a RTP reactor where wafer temperature is measured by a pyrometer assembly (32), a pyrometer assembly (50) is further provided to measure the temperature of the quartz window (30) that is situated between the wafer pyrometer assembly (32) and the wafer (16) that is being processed. During the cali ...


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Mark S Rodder, Richard A Chapman: Method of forming a MOSFET using a disposable gate and raised source and drain. Texas Instruments Incorporated, Jacqueline J Garner, Wade James Brady, Frederick J Telecky Jr, May 16, 2000: US06063677 (47 worldwide citation)

A method for forming a MOSFET transistor (100) using a disposable gate (120). A disposable gate (120) having at least two materials (122,124) that may be etched selectively with respect to each other is formed on a semiconductor substrate (102). Source/drain regions (104) are then formed adjacent th ...


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Theodore W Houston: SPIMOX/SIMOX combination with ITOX option. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Frederick J Telecky Jr, October 8, 2002: US06461933 (46 worldwide citation)

Beam implantation is combined with plasma implantation of oxygen, and possibly also internal thermal oxidation, to form a high quality buried oxide layer.


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Mark R Visokay, Luigi Colombo, James J Chambers, Antonio L P Rotondaro, Haowen Bu: Method for fabricating transistor gate structures and gate dielectrics thereof. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Frederick J Telecky Jr, November 14, 2006: US07135361 (45 worldwide citation)

Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the ...


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Satwinder Malhi: Top-drain trench based resurf DMOS transistor structure. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Richard L Donaldson, March 3, 1998: US05723891 (43 worldwide citation)

A top drain trench based RESURF DMOS (reduced surface field double diffused MOS) transistor structure provides improved RDSon performance by minimizing transistor cell pitch. The transistor includes a gate, a source and drain. The trench may include a nonuniform dielectric lining. A drain drift regi ...


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Yong J Lee, Mehrdad M Moslehi: Multi-zone lamp interference correction system. Texas Instruments Incorporated, Jacqueline J Garner, Richard L Donaldson, William E Hiller, August 22, 1995: US05444815 (42 worldwide citation)

A multi-zone lamp interference correction system and method for accurate pyrometry-based multi-point wafer temperature measurement in a multi-zone rapid thermal processing system comprises a plurality of lamps arranged in zones. A dummy lamp is also provided for each zone. Each lamp heating zone and ...