1
Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, July 28, 2015: US09093298 (5 worldwide citation)

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


2
Eb Eshun
Ebenezer Eshun: Structure and method for integrating front end SiCr resistors in HiK metal gate technologies. Texas Instruments Incorporated, Jacqueline J Garner, Wade J Brady III, Frederick J Telecky Jr, March 25, 2014: US08680618 (4 worldwide citation)

An integrated circuit having a replacement HiK metal gate transistor and a front end SiCr resistor. The SiCr resistor replaces the conventional polysilicon resistor in front end processing and is integrated into the contact module. The first level of metal interconnect is located above the SiCr resi ...


3
Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, December 1, 2015: US09202883 (1 worldwide citation)

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


4
Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, August 2, 2016: US09406769

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


5
Eb Eshun
Himadri Sekhar Pal, Ebenezer Eshun, Shashank S Ekbote: Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, December 29, 2015: US09224653

In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional ma ...


6
Eb Eshun
Ebenezer Eshun: Method to enable higher carbon co-implants to improve device mismatch without degrading leakage. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, August 30, 2016: US09431533

An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo implants. The carbon is co-implanted at tilt angles within 5 degrees of the boron halo implant tilt angle. An implant energy of at least on ...


7
Eb Eshun
Himadri Sekhar Pal, Ebenezer Eshun, Shashank S Ekbote: Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank Cimino, July 7, 2015: US09076670

In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional ma ...


8
Zhiqiang Wu: Self-aligned resistive plugs for forming memory cell with phase change material. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Frederick J Telecky Jr, April 8, 2003: US06545903 (240 worldwide citation)

Memory devices are disclosed for storage and retrieval of information, wherein resistive plugs are provided above and below a phase change material to form a memory cell. The plugs may be formed by implanting regions in high resistivity material above and below a phase change material layer to lower ...


9
Mehrdad M Moslehi: Low-temperature in-situ dry cleaning process for semiconductor wafer. Texas Instruments Incorporated, Jacqueline J Garner, Richard L Donaldson, William E Hiller, April 4, 1995: US05403434 (222 worldwide citation)

A low-temperature (350.degree. C. to 750.degree. C.) in-situ dry cleaning process for removing native oxide (and other contaminants) from a semiconductor wafer surface, that can be used with either batch or single-wafer semiconductor device manufacturing reactors. A wafer is contacted with a dry cle ...


10
Shivaling S Mahant Shetti, Derek J Smith, Basavaraj I Pawate, George R Doddington, Warren L Bean, Mark G Harward, Thomas J Aton: Distributed processing memory chip with embedded logic having both data memory and broadcast memory. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Richard L Donaldson, May 12, 1998: US05751987 (200 worldwide citation)

Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data me ...