1
Eb Eshun
Anil K Chinthakindi, Timothy J Dalton, Ebenezer E Eshun, Jeffrey P Gambino, Anthony K Stamper, Kunal Vaed: Methods of fabricating passive element without planarizing and related semiconductor device. International Business Machines Corporation, Lisa Jaklitsch, Hoffman Warnick, July 1, 2008: US07394145 (5 worldwide citation)

Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active c ...


2
Katherina Babich
Katherina E Babich, Scott D Halle, David V Horak, Arpan P Mahorowala, Wesley C Natzle, Dirk Pfeiffer, Hongwen Yan: Etch selectivity enhancement for tunable etch resistant anti-reflective layer. International Business Machines Corporation, Yuanmin Cai Esq, Hoffman Warnick & D Alessandro, July 18, 2006: US07077903 (4 worldwide citation)

Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA laye ...


3
Eb Eshun
Douglas D Coolbaugh, Timothy J Dalton, Daniel C Edelstein, Ebenezer E Eshun, Jeffrey P Gambino, Kevin S Petrarca, Anthony K Stamper, Richard P Volant: Planar vertical resistor and bond pad resistor. International Business Machines Corporation, Lisa U Jaklitsch, Hoffman Warnick, July 1, 2008: US07394110 (4 worldwide citation)

Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor inc ...


4
Eb Eshun
Douglas D Coolbaugh, Timothy J Dalton, Daniel C Edelstein, Ebenezer E Eshun, Jeffrey P Gambino, Kevin S Petrarca, Anthony K Stamper, Richard P Volant: Planar vertical resistor and bond pad resistor and related method. International Business Machines Corporation, Hoffman Warnick, Lisa Jaklitsch, May 5, 2009: US07528048 (4 worldwide citation)

Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor inc ...


5
Eb Eshun
Anil K Chinthakindi, Timothy J Dalton, Ebenezer E Eshun, Jeffrey P Gambino, Anthony K Stamper, Kunal Vaed: Methods of fabricating passive element without planarizing. International Business Machines Corporation, Lisa U Jaklitsch, Hoffman Warnick & D Alessandro, September 23, 2008: US07427550 (3 worldwide citation)

Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active c ...


6
Katherina Babich
Katherina Babich, Todd C Bailey, Richard A Conti, Ryan P Deschner: Mask forming and implanting methods using implant stopping layer and mask so formed. International Business Machines Corporation, Wenjie Li, Hoffman Warnick, January 26, 2010: US07651947 (2 worldwide citation)

Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: ...


7
Eb Eshun
Douglas D Coolbaugh, Ebenezer E Eshun, Robert M Rassel, Anthony K Stamper: MIM capacitor structure in FEOL and related method. International Business Machines Corporation, David Cain, Hoffman Warnick, February 28, 2012: US08125049 (1 worldwide citation)

A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor ...


8
Eb Eshun
Douglas D Coolbaugh, Ebenezer E Eshun, Robert M Rassel, Anthony K Stamper: Method of forming MIM capacitor structure in FEOL. International Business Machines Corporation, David A Cain, Hoffman Warnick, December 17, 2013: US08609505

A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor ...


9
Eb Eshun
Anil K Chinthakindi, Timothy J Dalton, Ebenezer E Eshun, Jeffrey P Gambino, Anthony K Stamper, Kunal Vaed: Methods of fabricating passive element without planarizing and related semiconductor device. International Business Machines Corporation, Katherine S Brown, Hoffman Warnick, February 21, 2012: US08119491

Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active c ...


10
Eb Eshun
Anil K Chinthakindi, Timothy J Dalton, Ebenezer E Eshun, Jeffrey P Gambino, Anthony K Stamper, Kunal Vaed: Methods of fabricating passive element without planarizing and related semiconductor device. International Business Machines Corporation, Hoffman Warnick, Katherine S Brown, July 16, 2013: US08487401

Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active c ...