1
Charles William Eichelberger: Single chip modules, repairable multichip modules, and methods of fabrication thereof. EPIC Technologies, Heslin & Rothenberg P C, November 24, 1998: US05841193 (432 worldwide citation)

Multichip and single chip modules are presented as well as a chips first fabrication of such modules. The multichip module comprises a plurality of chips affixed in a planar array by a structural material which surrounds the sides of the chips such that the upper surfaces of the chips and an upper s ...


2
Joseph Andrew Iadanza: System and method for dynamically reconfiguring a programmable gate array. International Business Machines Corporation, Susan M Murray Esq, Heslin & Rothenberg P C, July 8, 1997: US05646544 (303 worldwide citation)

In each of multiple logic cells of a Programmable Gate Array ("PGA"), a programing array is provided having multiple programming words therein. Each of the programming words is engagable to control the configuration of the logic cell. The programming words are selectively engaged such that multiple ...


3
David John Craft, Scott Whitney Gould, Frank Ray Keyser III, Brian Worth: Method and system for programming a gate array using a compressed configuration bit stream. International Business Machines Corporation, Heslin & Rothenberg P C, April 28, 1998: US05745734 (222 worldwide citation)

A generalized data decompression engine is incorporated within a field programmable gate array ("FPGA"). The generalized data decompression engine uses a general purpose data decompression technique such as, for example, a Lempel-Ziv type technique. During operation, a compressed configuration bit s ...


4
Michael J Laramie: Interconnect structure between heterogeneous core regions in a programmable array. International Business Machines Corporation, Heslin & Rothenberg P C, April 25, 2000: US06054873 (191 worldwide citation)

A programmable interconnect structure is provided whereby core regions of an integrated circuit having circuits of different functional types therein are connected. Ports are defined in a first core region along its boundary with a second core region, and port multiplexers selectively provide signal ...


5
Mark Louis Ciacelli, John William Urda, Wai Man Lam, Jack Lawrence Kouloheris, John Edward Fetkovich: Apparatus, method and computer program product for protecting copyright data within a computer system. International Business Machines Corporation, William H Steinberg, Heslin & Rothenberg P C, May 22, 2001: US06236727 (191 worldwide citation)

Apparatus, method and computer program product are provided for digitally processing an encrypted data stream scrambled, for example, according to content scrambling system (CSS) technology. This digital processing insures against communication of clear data within the computer system from a central ...


6
Claude Louis Bertin, John Edward Cronin: Programmable logic array. International Business Machines Corporation, Wayne F Reinke Esq, Heslin& Rothenberg P C, July 14, 1998: US05781031 (181 worldwide citation)

A programmable logic array (PLA) includes two direct-write EEPROM arrays, and PLA logic circuitry, such as feedback, drivers and input and output circuitry. One EEPROM array acts as an AND array and the other acts as n OR array. The PLA can be used for a memory function or a PLA function. In one asp ...


7
Charu Chandra Aggarwal, Joel Leonard Wolf, Philip Shi lung Yu: System and method for construction of a data structure for indexing multidimensional objects. International Business Machines Corporation, Heslin & Rothenberg P C, July 14, 1998: US05781906 (179 worldwide citation)

An apparatus and a method for constructing a multidimensional index tree which minimizes the time to access data objects and is resilient to the skewness of the data. This is achieved through successive partitioning of all given data objects by considering one level at a time starting with one parti ...


8
Charles William Eichelberger: Single chip modules, repairable multichip modules, and methods of fabrication thereof. EPIC Technologies, Heslin & Rothenberg P C, December 12, 2000: US06159767 (176 worldwide citation)

Multichip and single chip modules are presented as well as a chips first fabrication of such modules. The multichip module comprises a plurality of chips affixed in a planar array by a structural material which surrounds the sides of the chips such that the upper surfaces of the chips and an upper s ...


9
Scott Whitney Gould, Frank Ray Keyser III, Wendell Ray Larsen, Brian Allen Worth: Programmable array interconnect latch. International Business Machines Corporation, Heslin & Rothenberg P C, March 24, 1998: US05732246 (174 worldwide citation)

A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of ...


10
Amir Hekmatpour: Adaptive hypermedia presentation method and system. International Business Machines Corporation, Heslin & Rothenberg P C, August 25, 1998: US05799292 (170 worldwide citation)

In a computer system comprising a hypermedia computing environment, the presentation of hypermedia objects is adapted to usage of the system. The frequency with which hypermedia objects are used is tracked and the objects are ordered such that the most frequently used hypermedia objects are made mos ...



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