11
K Paul L Muller, Edward J Nowak, Hon Sum P Wong: Planarized silicon fin device. International Business Machines Corporation, H Daniel Schnurmann, Ratner & Prestia, June 26, 2001: US06252284 (150 worldwide citation)

An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the ...


12
Hiroyuki Akatsu, Tze Chiang Chen, Laertis Economikos, Herbert L Ho, Richard Kleinhenz, Jack A Mandelman, Wesley C Natzle: Structure and method for producing low leakage isolation devices. International Business Machines Corporation, H Daniel Schnurmann, Ratner & Prestia, November 20, 2001: US06319794 (131 worldwide citation)

A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The in ...


13
Richard P Volant, David Angell, Donald F Canaperi, Joseph T Kocis, Kevin S Petrarca, Kenneth J Stein, William C Wille: Micro electromechanical switch having self-aligned spacers. International Business Machines Corporation, H Daniel Schnurmann, September 16, 2003: US06621392 (129 worldwide citation)

A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems cau ...


14
Timothy J Dalton, John P Hummel: Post metalization chem-mech polishing dielectric etch. International Business Machines Corporation, H Daniel Schnurmann, April 22, 2003: US06551924 (124 worldwide citation)

A method for etching an insulating layer without damage to the conducting layer and associated liner layer within the insulating layer. A dielectric layer is deposited on a semiconductor substrate and then patterned. A liner layer and a conducting layer are then deposited within the patterned dielec ...


15
Diane C Boyd, Judson R Holt, MeiKei Ieong, Renee T Mo, Zhibin Ren, Ghavam G Shahidi: Ultra-thin body super-steep retrograde well (SSRW) FET devices. International Business Machines Corporation, Graham S Jones II, H Daniel Schnurmann, February 21, 2006: US07002214 (120 worldwide citation)

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. ...


16
Yaocheng Liu, Subramanian S Iyer, Jinghong Li: Low defect Si:C layer with retrograde carbon profile. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, April 13, 2010: US07696000 (106 worldwide citation)

Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concent ...


17
Huajie Chen, Dureseti Chidambarrao, Oleg G Gluschenkov, An L Steegen, Haining S Yang: Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions. International Business Machines Corporation, Daryl K Neff, H Daniel Schnurmann, May 10, 2005: US06891192 (105 worldwide citation)

A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain ...


18
Fariborz Assaderaghi, Tze Chiang Chen, K Paul Muller, Edward Joseph Nowak, Devendra Kumar Sadana, Ghavam G Shahidi: Double SOI device with recess etch and epitaxy. International Business Machines Corporation, H Daniel Schnurmann, Scully Scott Murphy & Presser, August 13, 2002: US06432754 (104 worldwide citation)

The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area bet ...


19
Huilong Zhu, Effendi Leobandung, Anda C Mocuta, Dan M Mocuta: MOSFET with super-steep retrograded island. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, May 25, 2010: US07723750 (102 worldwide citation)

The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; et ...


20
Stephen M Rooks: Inspection system for cross-sectional imaging. International Business Machines Corporation, H Daniel Schnurmann, January 7, 1997: US05592562 (99 worldwide citation)

A method and apparatus for inspecting a bonded joint between components. A cross-sectional image of the joint is analyzed by determining the location of a first characteristic of the joint, the centroid of the joint in the cross-sectional image; and then measuring a second characteristic of the join ...