1
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, H Daniel Schnurmann, May 20, 2008: US07374987 (17 worldwide citation)

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


2
Eb Eshun
Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, Keith Edward Downes, Ebenezer E Eshun, Zhong Xiang He, Robert Mark Rassel, Anthony Kendall Stamper, Kunal Vaed: Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric. International Business Machines Corporation, H Daniel Schnurmann, Graham S Jones II, April 22, 2008: US07361950 (10 worldwide citation)

A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower ...


3
Eb Eshun
Thomas A Wallner, Ebenezer E Eshun, Daniel J Jaeger, Phung T Nguyen: Method of forming bipolar transistor integrated with metal gate CMOS devices. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, March 6, 2012: US08129234 (5 worldwide citation)

A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction tr ...


4
Eb Eshun
Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, Keith Edward Downes, Ebenezer E Eshun, Zhong Xiang He, Robert Mark Rassel, Anthony Kendall Stamper, Kunal Vaed: Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material. International Business Machines Corporation, H Daniel Schnurmann, Graham S Jones, March 29, 2011: US07915134 (1 worldwide citation)

A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower ...


5
Eb Eshun
Thomas A Wallner, Ebenezer E Eshun, Daniel J Jaeger, Phung T Nguyen: Bipolar transistor integrated with metal gate CMOS devices. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, October 29, 2013: US08569840

A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction tr ...


6
Ka Hing Fung, H Bernhard Pogge: Three-dimensional chip stacking assembly. International Business Machines Corporation, H Daniel Schnurmann, March 12, 2002: US06355501 (386 worldwide citation)

An assembly consisting of three dimensional stacked SOI chips, and a method of forming such integrated circuit assembly, each of the SOI chips including a handler making mechanical contact to a first metallization pattern making electrical contact to a semiconductor device. The metalized pattern, in ...


7
Joseph M Crichton, Peter F Garvin, Jeffrey W Staten, Waiki L Wright: Method and apparatus for lightweight secure communication tunneling over the internet. International Business Machines Corporation, H Daniel Schnurmann Esq, Whitham Curtis & Whitham, August 15, 2000: US06104716 (256 worldwide citation)

A lightweight secure tunneling protocol or LSTP permits communicating across one or more firewalls by using a middle server or proxy. Three proxies are used to establish an end-to-end connection that navigates through the firewalls. In a typical configuration, a server is behind a first firewall and ...


8
Larry Clevenger, Louis L C Hsu, Chandrasekhar Narayan, Jeremy K Stephens, Michael Wise: Fuse processing using dielectric planarization pillars. International Business Machines Corporation, Infineon Technologies North America, Peter W Peterson, H Daniel Schnurmann, Delio & Peterson, July 16, 2002: US06420216 (213 worldwide citation)

An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further ele ...


9
Lars Wolfgang Liebmann, Robert Thomas Sayah, John Edward Barth Jr: Fidelity enhancement of lithographic and reactive-ion-etched images by optical proximity correction. International Business Machines Corporation, H Daniel Schnurmann, April 14, 1998: US05740068 (197 worldwide citation)

A method for performing optical proximity correction is disclosed that not only limits the optical proximity correction to electrically relevant structures, but also improves the accuracy of the corrections by processing individual feature edges, and minimizes the mask manufacturing impacts by avoid ...


10
Carl J Radens, Gary B Bronner, Tze chiang Chen, Bijan Davari, Jack A Mandelman, Dan Moy, Devendra K Sadana, Ghavam Ghavami Shahidi, Scott R Stiffler: Silicon-on-insulator vertical array device trench capacitor DRAM. International Business Machines Corporation, H Daniel Schnurmann, May 20, 2003: US06566177 (165 worldwide citation)

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate ...