1
Crane John R, Lawson James C, Petschauer Richard J: Flexible carrier and interconnect for uncased ic chips. Sperry Rand Corporation, Grace Kenneth T, Nikolai Thomas J, Dority John P, October 1, 1974: US3838984 (265 worldwide citation)

A printed circuit lead frame that functions as a carrier of an integrated circuit (IC) uncased chip for initial handling and testing and later as a means for bonding the chip's contacts to printed circuitry on a supporting substrate is disclosed. The lead frame includes a flexible insulating sheet m ...


2
Alferness Merwin H, Miller John A: Common storage controller for dual processor system. Sperry Rand Corporation, Nikolai Thomas J, Grace Kenneth T, Truex Marshall M, June 10, 1975: US3889237 (82 worldwide citation)

Control devices for permitting two or more general purpose digital computers, each with its own main storage module, to share a common data base. The control devices, termed 'Common Storage Controller(s)' contain the logic circuitry for interfacing the central processors to their storage units such ...


3
MacDonald Thomas Richard: Multi-processor system with multiple cache memories. Sperry Rand Corporation, Nikolai Thomas J, Grace Kenneth T, Dority John P, November 12, 1974: US3848234 (52 worldwide citation)

A digital data multi-processing system having a main memory operating at a first rate, a plurality of individual processors, each having its own associated cache memory operating at a second rate substantially faster than the first rate for increasing the throughput of the system. In order to contro ...


4
Scheuneman James H, Trost John R: Error logging in LSI memory storage units using FIFO memory of LSI shift registers. Sperry Rand Corporation, Grace Kenneth T, Nikolai Thomas J, Truex Marshall M, November 4, 1975: US3917933 (43 worldwide citation)

A maintenance procedure comprising a method of and an apparatus for storing information identifying the location of one or more defective bits, i.e., a defective memory element, a defective storage device or a failure, in a single-error-correcting semiconductor main storage unit (MSU) comprised of a ...


5
Torok Ernest J: Programmable diffraction grating. Sperry Rand Corporation, Grace Kenneth T, Nikolai Thomas J, Truex Marshall M, January 21, 1975: US3861784 (42 worldwide citation)

An electrically alterable apparatus and method of operation thereof that permits the optical processing of an image is disclosed. The apparatus includes an array of optical cells comprised of a plurality of XY stripline arrays and a stripedomain film element. The stripe-domain wall separation and wa ...


6
Boss Garold D, Crane Vaemond H, McBeath Donald G, Thompson Martin D: Processor state and storage limits register auto-switch. Sperry Rand Corporation, Grace Kenneth T, Grace Kenneth J, Dority John P, June 4, 1974: US3815101 (29 worldwide citation)

A means for automatically changing from a first to a second processor state register (PSR) when the relative address represented by the base value contained in the first of the PSR's does not fall within first predetermined limits. Logic means respond to such limits test failure to automatically swi ...


7
Anderson Bruce M: Character generator for a high resolution dot matrix display. Sperry Rand Corporation, Nikolai Thomas J, Grace Kenneth T, Truex Marshall M, November 18, 1975: US3921164 (29 worldwide citation)

A character generator for a dot-matrix type alpha-numeric display device whereby the resolution of the characters to be displayed is greatly increased without a corresponding increase in the size of the Read-Only Memory (ROM) utilized to store the dot patterns defining the characters to be formed. T ...


8
Eberlein Delvin D, Englund Robert M: Concurrent data address and refresh control for a volatile lsi memory system. Sperry Rand Corporation, Grace Kenneth T, Nikolai Thomas J, Truex Marshall M, January 7, 1975: US3859640 (29 worldwide citation)

A novel internal organization of an LSI memory chip for optimum refresh control is disclosed. The chip is organized in a plurality of N similar memory loops in which the M data bits that are stored in each memory loop are serially shifted therethrough in an end-around fashion for the data reading, w ...


9
Ellison James T: Nth power galois linear gate. Grace Kenneth T, Nikolai Thomas J, April 16, 1974: US3805037 (24 worldwide citation)

A configuration of two-level Boolean elements for implementing an n'th power Galois linear gate on a single medium scale integrated circuit chip is disclosed. The illustrated configuration includes orthogonally arranged sets of four parallel X input lines and four parallel Y input lines having each ...


10
Boles John A, Chu Charles M, Criswell Peter B, Rolnitzky Aron: System for conversion between coded byte and floating point format. Sperry Rand Corporation, Nikolai Thomas J, Grace Kenneth T, Truex Marshall M, March 18, 1975: US3872442 (21 worldwide citation)

Conversion circuitry for converting coded byte strings representative of floating-point numbers to single-precision or double-precision binary floating-point number equivalents, and conversion circuitry for converting single-precision of double-precision binary floating-point numbers to coded byte s ...