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Eugene Fitzgerald
Eugene A Fitzgerald: Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization. Massachusetts Institute of Technology, Goodwin Procter, July 31, 2007: US07250359 (60 worldwide citation)

A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the inve ...


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Eugene Fitzgerald
Zhi Yuan Cheng, Eugene A Fitzgerald, Dimitri A Antoniadis, Judy L Hoyt: Process for producing semiconductor article using graded epitaxial growth. Massachusetts Institute of Technology, Goodwin Procter, July 26, 2005: US06921914 (34 worldwide citation)

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydr ...


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Eugene Fitzgerald
Matthew T Currie, Anthony J Lochtefeld, Christopher W Leitz, Eugene A Fitzgerald: Semiconductor devices having strained dual channel layers. AmberWave Systems Corporation, Goodwin Procter, November 21, 2006: US07138310 (27 worldwide citation)

A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentrati ...


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Eugene Fitzgerald
Eugene A Fitzgerald: Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits. AmberWave Systems Corporation, Goodwin Procter, August 14, 2007: US07256142 (26 worldwide citation)

Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to ...


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Eugene Fitzgerald
Eugene A Fitzgerald: Buried channel strained silicon FET using a supply layer created through ion implantation. AmberWave Systems Corporation, Goodwin Procter, November 29, 2005: US06969875 (24 worldwide citation)

A buried channel FET including a substrate, a relaxed SiGe layer, a channel layer, a SiGe cap layer, and an ion implanted dopant supply. The ion implanted dopant supply can be in either the SiGe cap layer or the relaxed SiGe layer. In one embodiment the FET is a MOSFET. In another embodiment the FET ...


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Eugene Fitzgerald
Kenneth C Wu, Eugene A Fitzgerald, Gianni Taraschi, Jeffrey T Borenstein: Etch stop layer system. Massachusetts Institute of Technology, The Charles Stark Draper Laboratory, Goodwin Procter, June 5, 2007: US07227176 (15 worldwide citation)

A semiconductor structure including a uniform etch-stop layer. The uniform etch stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×1019 boron atoms/cm3. A method for forming a semiconductor structure includes forming a uniform etch-stop lay ...