1
Chen Chung Hsu: Three-dimensional multichip package. United Microelectronics Corporation, George O Saile, Wolmar Stoffel, January 2, 1996: US05481133 (329 worldwide citation)

A multichip array package for IC devices with a master semiconductor device supporting and electrically interconnected with a stacked array of subordinate devices. The interconnection structure has a peripheral row of contact pads on the master device. The subordinate devices each have a peripheral ...


2
Francisca Tung: Pillar connections for semiconductor chips and method of manufacture. Advanpack Solutions, George O Saile, Stephen B Ackerman, June 17, 2003: US06578754 (278 worldwide citation)

A flip chip interconnect system comprises and elongated pillar comprising two elongated portions, one portion including copper and another portion including solder. The portion including copper is in contact with the semiconductor chip and has a length preferably of more than 55 microns to reduce th ...


3
Yee Chia Yeo, Fu Liang Yang, Chenming Hu: Method of forming a transistor with a strained channel. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, December 10, 2002: US06492216 (273 worldwide citation)

A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method features the epitaxial growth of a semiconductor la ...


4
Siang Tze Reginald Wee, Jie Liang: 3-D image detector. Tritech Mircoelectronics International, George O Saile, Stephen B Ackerman, Bill Knowles, March 2, 1999: US05877803 (272 worldwide citation)

A three dimensional image detector is disclosed. The three dimensional image detector has a lensing system to focus incident light reflected from an object field upon a first and second image detector. The first and second image detectors are matrices of charge coupled devices. The first and second ...


5
Hans Joachim Trumpp, Johann Greschner: Method of making structures with dimensions in the sub-micrometer range. International Business Machines Corporation, George O Saile, March 5, 1985: US04502914 (260 worldwide citation)

Following the method of making structures with dimensions in the submicrometer range, structures of a polymeric layer with horizontal and substantially vertical surfaces are first made on a substrate. Thereupon, a silicon nitride or oxide layer is plasma deposited. This layer is subjected to reactiv ...


6
Jacob Riseman, Paul J Tsang: Fabrication process of sub-micrometer channel length MOSFETs. International Business Machines Corporation, George O Saile, December 13, 1983: US04419809 (253 worldwide citation)

Methods for fabricating a semiconductor integrated circuit having a sub-micrometer gate length field effect transistor devices are described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor from one another. Certain of these semic ...


7
Chen Chung Hsu: Three-dimensional multichip package and methods of fabricating. United Microelectronics Corporation, George O Saile, Wolmar J Stoffel, January 10, 1995: US05380681 (239 worldwide citation)

A process for fabricating a three-dimensional multi-chip array package wherein master semiconductor substrate is formed having a peripheral inner row of contact pads and a peripheral outer row of terminal pads. A plurality of subordinate semiconductor substrates are formed provided with a peripheral ...


8
Sik On Kong: Three dimensional IC package module. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, March 25, 2003: US06538333 (238 worldwide citation)

In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling ...


9
Jacob Riseman: Method for forming an insulator between layers of conductive material. International Business Machines Corporation, George O Saile, November 18, 1980: US04234362 (229 worldwide citation)

A method for forming an insulator between conductive layers, such as highly doped polycrystalline silicon, that involves first forming a conductive layer of, for example, polycrystalline silicon on a silicon body having substantially horizontal and substantially vertical surfaces. A conformal insula ...


10
Chih Yuan Lu, Janmye Sung: Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits. Vanguard International Semiconductor Corporation, George O Saile, Stephen B Ackerman, August 24, 1999: US05943581 (226 worldwide citation)

An improved DRAM cell using a novel buried reservoir capacitor is achieved. The method forms an array of N.sup.+ doped regions in a substrate. P-wells are formed in an epitaxy layer on the substrate. A field oxide (FOX) is formed surrounding the device areas aligned over the N.sup.+ regions. Holes a ...



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