21
Thanomsak Sankhagowit: Pre-testable semiconductor die package. National Semiconductor Corporation, Gail W Woodward, October 20, 1987: US04701781 (61 worldwide citation)

An encapsulated die package (20) is shown in which a semiconductor die is connected in a die-attach aperture of a copper foil tape (11). Die contact pads (31) are bonded to the inner ends (31a) of interconnected finger contacts (13) on the tape. Finger contacts etched in the foil include splayed out ...


22
Robert C Byrne, Jon T Ewanich, Chee Men Yu: Ceramic lid hermetic seal package structure. National Semiconductor Corporation, Gail W Woodward, Lee Patch, Mark Aaker, September 6, 1988: US04769272 (57 worldwide citation)

A sidebrazed ceramic package is provided with a closure seal that employs a high alumina ceramic lid that matches the composition of the package body. The lid is provided with a recess in the sealing face and the sealing face is provided with metallization that adheres to the ceramic and is wet by s ...


23
Chok J Chia: Plastic molded pin-grid-array power package. National Semiconductor Corporation, Gail W Woodward, Lee Patch, September 19, 1989: US04868349 (56 worldwide citation)

A molded pin-grid-array package includes a heat sink available at the face opposite to the pins. The heat sink is secured to a printed wiring board that has plated through holes therein that form the desired pin-grip-array and wires are secured in the holes to form the package pins. The heat sink co ...


24
Carmen D Burns: Tape operated semiconductor device packaging. National Semiconductor Corporation, Gail W Woodward, James A Sheridan, Neil B Schulte, May 18, 1982: US04330790 (54 worldwide citation)

A semiconductor device is bonded to a contact finger pattern which is located in a continuous tape. A metal package cup is fabricated from metal stock so as to have a flat rim portion around its periphery. A plastic insulating sheet is punched so that it forms an overlapping cover for the flat rim a ...


25
Thomas P Redfern: Trim structure for integrated capacitors. National Semiconductor Corporation, Gail W Woodward, February 26, 1980: US04190854 (53 worldwide citation)

A capacitor suitable for integration into a monolithic integrated circuit is fabricated in two parallel connected sections. One section, using a thin oxide, constitutes most of the capacitance. A second section fabricated on a thick oxide constitutes a smaller capacitance per unit area but can be la ...


26
Frederick J Smith: Programmable fuse circuit. National Semiconductor Corporation, Gail W Woodward, Paul J Winters, Michael J Pollock, May 1, 1984: US04446534 (53 worldwide citation)

A programmable fuse circuit has a fusable polysilicon element programmable in response to an "illegal" condition on existing pins of an integrated circuit. This programmable fuse circuit is incorporated in a programmable partial memory circuit, a reconfigurable format memory circuit, and a chip sele ...


27
Yoav Lavi: Content-addressable memory. National Semiconductor Corporation, Gail W Woodward, Paul J Winters, Neil B Schulte, March 22, 1983: US04377855 (52 worldwide citation)

A content-addressable memory (CAM) has an array of four-transistor memory cells arranged in rows corresponding to stored words and columns corresponding to a selected search word. Complementary column lines couple signals associated with the bits of the search word to the memory cells associated wit ...


28
David F Hebert: Semiconductor package with tape mounted die. National Semiconductor Corporation, Gail W Woodward, March 10, 1987: US04649415 (51 worldwide citation)

A semiconductor package has a molded-in-place lead frame (15) resting on a ledge (12b) adjacent a die-receiving trough (13) in a molded housing (10). A one-layer or two-layer flexible tape includes a depending tab (22) on which a die (30) is bonded and positioned within the trough. Electrical bonds ...


29
Chenming Hu, Steven P Sapp: High voltage power IC process. National Semiconductor Corporation, Gail W Woodward, Lee Patch, Michael A Glenn, March 13, 1990: US04908328 (51 worldwide citation)

A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage trans ...


30
Ramanatha V Balakrishnan: Active bus backplane. National Semiconductor Corporation, Gail W Woodward, October 6, 1987: US04697858 (51 worldwide citation)

A digital bus backplane is disclosed that has interface circuitry located on the backplane. The backplane includes a backplane circuit board containing signal bus lines each operable for conducting electrical signals, several connectors each physically coupled to the backplane circuit board and each ...