1
Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, July 28, 2015: US09093298 (5 worldwide citation)

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


2
Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, December 1, 2015: US09202883 (1 worldwide citation)

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


3
Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, August 2, 2016: US09406769

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


4
Eb Eshun
Himadri Sekhar Pal, Ebenezer Eshun, Shashank S Ekbote: Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, December 29, 2015: US09224653

In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional ma ...


5
Eb Eshun
Ebenezer Eshun: Method to enable higher carbon co-implants to improve device mismatch without degrading leakage. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, August 30, 2016: US09431533

An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo implants. The carbon is co-implanted at tilt angles within 5 degrees of the boron halo implant tilt angle. An implant energy of at least on ...


6
David Grant: Frequency control of hysteretic power converter by adjusting hystersis levels. Texas Instruments Incorporated, Frank D Cimino, W James Brady, Frederick J Telecky Jr, February 19, 2002: US06348780 (141 worldwide citation)

A power converter is comprised of a hysteretic controller including a feedback circuit that monitors the output frequency of the controller, compares it to a reference generated either internally or externally by the user, and then adjusts the hysteresis of the controller accordingly. The adjusted h ...


7
Juan Alejandro Herbsommer, Gerd Schuppener, Robert Floyd Payne: Dielectric waveguide with non-planar interface surface and mating deformable material. Texas Instruments Incorporated, Lawrence J Bassuk, Frank D Cimino, May 24, 2016: US09350063 (105 worldwide citation)

A dielectric wave guide (DWG) has a dielectric core member having that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured in a non-plan ...


8
Juan Alejandro Herbsommer, Robert Floyd Payne, Gerd Schuppener, Baher Haroun: Radiating sub-terahertz signal from tapered metallic waveguide into dielectric waveguide. Texas Instruments Incorporated, Lawrence J Bassuk, Frank D Cimino, December 6, 2016: US09515367 (72 worldwide citation)

A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the ...


9
Jin Liu: Self-isolating mixed design-rule integrated yield monitor. TEXAS INSTRUMENTS INCOPORATED, Jacqueline J Garner, Frank D Cimino, December 29, 2015: US09222969 (64 worldwide citation)

Assessing open circuit and short circuit defect levels in circuits implemented in state of the art ICs is difficult when using conventional test circuits, which are designed to assess continuity and isolation performance of simple structures based on individual design rules. Including circuit blocks ...


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Ananth Somayaji, Sourav Modi, Sani Dewal, Saravanan Ambikapathy: Filler insertion in circuit layout. TEXAS INSTRUMENTS INCORPORATED, John R Pessetto, Charles A Brill, Frank D Cimino, January 10, 2017: US09542521 (54 worldwide citation)

A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells is disclosed. First, a set of filler classes, each filler class having a set of filler cells, is classified that are configured to fill the gaps depending on a design requiremen ...