1
Edward B Knudson, David M Rudnick, Michael D Ellis, Daniel C Hagenbuch, Joel G Hassell, Robert A Knee, Steven J Reynolds: Program guide system with real-time data sources. United Video Properties, Richard M Feustel Jr, Evelyn C Mak, Fish & Neave, March 18, 2003: US06536041 (340 worldwide citation)

A program guide system is provided in which an interactive television program guide that is implemented at least partially on user television equipment receives program listings data and real-time data such as sports scores, news data, and the like. The real-time data may be stored in a database mai ...


2
Edward B Knudson, Joel G Hassell, Michael D Ellis, Pamela L McKissick: Enhanced interactive program guide. United Video Properties, Richard M Feustel Jr, Evelyn C Mak, Fish & Neave, February 25, 2003: US06526577 (278 worldwide citation)

An interactive television program guide system and method in which functions that have not been provided before by other interactive television program guide systems is provided. The interactive guide may, for example, provide users with an opportunity to preview pay-per-view programs before orderin ...


3
Masood Garahi, Connie T Marshall, William L Thomas: Systems and methods for cross-platform access to a wagering interface. ODS Properties, Fish & Neave, Evelyn C Mak, Adam M Saltzman, January 4, 2005: US06837789 (192 worldwide citation)

Systems and methods for providing a consistent wagering interface to a variety of platforms are presented. A wagerer may access wagering information using a set-top box, computer, wireless device, or telephone. A central database can be used to store and maintain the wagerer's preferences for the wa ...


4
Chiakang Sung, Robert R N Bielby, Richard G Cliff, Edward Aung: Phase-locked loop circuitry for programmable logic devices. Altera Corporation, Robert R Jackson, Evelyn C Mak, Fish & Neave, October 22, 2002: US06469553 (54 worldwide citation)

A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequ ...


5
Malik Kabani, Henry Lui: Programmable logic resource with data transfer synchronization. Altera Corporation, Fish & Neave IP Group Ropes & Gray, Evelyn C Mak, February 21, 2006: US07003423 (20 worldwide citation)

A more time-efficient and area-efficient approach is provided to synchronize the transfer of data into programmable logic resources. A programmable logic resource core clock and a reset signal are routed to a reset register that controls the reset of a dynamic phase alignment circuit and a data real ...


6
Seong hoon Lee: Digital delay-locked loop circuits with hierarchical delay adjustment. Micron Technology, Fish & Neave IP Group of Ropes & Gray, Evelyn C Mak, January 3, 2006: US06982578 (11 worldwide citation)

Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, the ...


7
Michael Shore, Brian P Callaway: Reducing digit equilibrate current during self-refresh mode. Micron Technology, Fish & Neave IP Group Ropes & Gray, Evelyn C Mak, September 20, 2005: US06947346 (10 worldwide citation)

Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a given row of memory cells refresh ...


8
John Lam, Arch Zaliznyak, Chong Lee, Rakesh Patel, Vinson Chan: Apparatus and method for reset distribution. Altera Corporation, Fish & Neave IP Group Ropes & Gray, Evelyn C Mak, April 11, 2006: US07028270 (8 worldwide citation)

A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerat ...


9
Michael Shore, Brian P Callaway: Reducing digit equilibrate current during self-refresh mode. Micron Technology, Garry J Tuma, Evelyn C Mak, Fish & Neave, March 23, 2004: US06711093 (8 worldwide citation)

Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a given row of memory cells refresh ...


10
Seong hoon Lee: Digital phase mixers with enhanced speed. Micron Technology, Fish & Neave IP Group of Ropes & Gray, Evelyn C Mak, October 4, 2005: US06952127 (7 worldwide citation)

Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select signals. The propagation delay of the output signal is reduced by using a first voltage source to drive the input signals and the output sign ...