41
John Z Colt Jr: Double silicon-on-insulator device and method therefor. International Business Machines Corporation, Eugene I Shkurko, Whitham Curtis & Whitham, January 11, 2000: US06013936 (40 worldwide citation)

An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes ...


42
Steven H Voldman, Robert J Gauthier Jr, Jeffrey S Brown: Semiconductor diode with depleted polysilicon gate structure and method. International Business Machines Corporation, Eugene I Shkurko, Whitham Curtis & Whitham, January 18, 2000: US06015993 (40 worldwide citation)

A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a ...


43
Michael M Walters: Method of making a monolithic magnetic device with printed circuit interconnections. International Business Machines, Eugene I Shkurko, William H Steinberg, January 30, 1996: US05487214 (40 worldwide citation)

A monolithic magnetic device having a plurality of transformer elements having single turn primaries and single turn secondaries fabricated on a plate of ferrite which has the outline of a ceramic leadless chip carrier. Each of the magnetic elements has a primary winding formed from a copper via pla ...


44
Frank W Brice Jr, Charles W Gainey Jr, Steven G Glassen, Marten J Halma, David W Hollar, Jeffrey P Kubala, Hans Helge Lehmann, Tan Lu, Michael G Melendy, Kenneth J Oakes, Charles E Shapley, Robert A Smith, John S Trotter, Leslie W Wyman, Harry M Yudenfriend: Method, system and program products for identifying communications adapters of a computing environment. International Business Machines Corporation, Eugene I Shkurko Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, October 31, 2006: US07130938 (39 worldwide citation)

An input/output subsystem of a computing environment is configured as a plurality of input/output subsystem images, each of which appears to a program as an independent input/output subsystem. An input/output subsystem image includes one or more communications adapters used for communicating within ...


45
John Edwin Gersbach: Pull-up and pull-down circuits. International Business Machines Corporation, Eugene I Shkurko, Schmeiser Olsen & Watts, February 29, 2000: US06031403 (39 worldwide citation)

According to the preferred embodiment of the present invention pull-up/pull-down circuits are provided that use transistors with different threshold voltages to assure power-up to the correct predetermined state. These circuits have the ability to hold a node up or down while drawing very little DC ...


46
Howard T Olnowich, Thomas N Barker, Peter M Kogge, Gilbert C Vandling III: Dual priority switching apparatus for simplex networks. International Business Machines, Eugene I Shkurko, Lynn L Augspurger, August 22, 1995: US05444705 (39 worldwide citation)

A high priority path is added to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as an output port ...


47
Robert D Adams, John Connor, Garrett S Koch, Luigi Ternullo Jr: Memory array built-in self test circuit for testing multi-port memory arrays. International Business Machines Corporation, Eugene I Shkurko, Schmeiser Olsen & Watts, August 18, 1998: US05796745 (39 worldwide citation)

A memory Array Built-In Self-Test (ABIST) circuit is disclosed that will test a multi-port memory array. A programmable pattern generator for the ABIST circuit allows for different R/W data operations to be performed at the same or adjacent address locations within a multi-port memory array. The pro ...


48
Diane C Boyd, Toshiharu Furukawa, Steven J Holmes, William H Ma, Paul A Rabidoux, David V Horak: Resist image reversal by means of spun-on-glass. International Business Machines Corporation, Eugene I Shkurko, April 24, 2001: US06221562 (39 worldwide citation)

An image reversal method of turning hybrid photoresist spaces into resist lines for sub-feature size applications. The sub-feature size space width of the high resolution hybrid photoresist is largely independent of the lithographic process and mask reticles. These sub-feature size spaces formed by ...


49
Edward Butler, Robert B Goodwin, Hemen R Shah, Robert Tamlyn: High performance extended data out. International Business Machines Corporation, Eugene I Shkurko, February 6, 1996: US05490114 (38 worldwide citation)

A high performance latch for read and write operations in RAM having a Complimentary Interlock circuit that eliminates the need for external timing to the RAM which might limit its high performance operation. For both read and write operations, the complementary interlock circuit extends a latching ...


50
Claude L Bertin, Russell J Houghton, Wilbur D Pricer, William R Tonti: Very low power logic circuit family with enhanced noise immunity. International Business Machines Corporation, Eugene I Shkurko Esq, Scully Scott Murphy & Presser, August 29, 2000: US06111425 (36 worldwide citation)

A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external nois ...



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