1
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, Jay H Anderson, Eugene I Shkurko, November 30, 2004: US06825529 (141 worldwide citation)

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


2
Ugochukwu Njoku
Ugochukwu Charles Njoku, Frank W Brice Jr, David Craddock, Richard K Errickson, Mark S Farrell, Charles W Gainey Jr, Donald W Schmidt, Gustav E Sittmann III: Virtualization of an I/O adapter port using enablement and activation functions. International Business Machines Corporation, Eugene I Shkurko, April 3, 2007: US07200704 (91 worldwide citation)

A method for configuring a communication port of a communications interface of an information handling system into a plurality of virtual ports. A first command is issued to obtain information indicating a number of images of virtual ports supportable by the communications interface. A second comman ...


3

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Ugochukwu Njoku
Frank W Brice Jr, Janet R Easton, Charles W Gainey Jr, Jeffrey P Kubala, Hans Helge Lehmann, Tan Lu, Ugochukwu Njoku Charles, Kenneth J Oakes, Dale F Riedy Jr, Charles E Shapley, Gustav E Sittmann, Leslie W Wyman, Harry M Yudenfriend: Managing sets of input/output communications subadapters of an input/output subsystem. International Business Machines Corporation, Eugene I Shkurko Esq, Blanch E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, October 2, 2007: US07277968 (35 worldwide citation)

Input/output (I/O) communications subadapters, such as subchannels, of an I/O subsystem are dedicated to components, such as I/O devices, of the I/O subsystem. The subadapters provide information about the associated components, in response to the execution of I/O instructions. To enhance I/O connec ...


5
Ugochukwu Njoku
Janet R Easton, Charles W Gainey, Tan Lu, Ugochukwu C Njoku, Gustav E Sittmann, Stephen G Wilkins, Frank W Brice, Damian L Osisek, Donald W Schmidt: Virtualization of infiniband host channel adapter interruptions. International Business Machines Corporation, Eugene I Shkurko, IBM Corp Intellectual Property Law, November 22, 2007: US20070271559-A1

A method, system, program product and computer data structure for providing for two levels of server virtualization. A first hypervisor enables multiple logical partitions to share a set of resources and provides a first level of virtualization. A second hypervisor enables multiple, independent virt ...


6
Joseph C Caci: Audio/video communications processor. International Business Machines, Eugene I Shkurko, Lynn L Augspurger, February 21, 1995: US05392223 (201 worldwide citation)

A communications processor serves a group of several workstations with audio and video transmission processing for the purpose of providing video conferencing. The communication processor utilizes artificial intelligence software to read the connection. Conversion rules are contained in tables so th ...


7
Gregory Costrini, Ronald Dean Goldblatt, John Edward Heidenreich III, Thomas Leddy McDevitt: Method/structure for creating aluminum wirebound pad on copper BEOL. International Business Machines Corporation, Eugene I Shkurko Esq, Scully Scott Murphy & Presser, February 13, 2001: US06187680 (181 worldwide citation)

The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the I ...


8
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Paul A Rabidoux: Method for forming pillar memory cells and device formed thereby. International Business Machines Corporation, Eugene I Shkurko, Schmeiser Olsen & Watts, August 1, 2000: US06096598 (136 worldwide citation)

The preferred embodiments of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity. In one embodiment, the present invention is used to form s ...


9
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, Michael E Whitham, Eugene I Shkurko, Mark F Chadurjian, November 19, 2002: US06483156 (132 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


10
Ramachandra Divakaruni, Russell J Houghton, Jack A Mandelman, W David Pricer, William R Tonti: Method for novel SOI DRAM BICMOS NPN. International Business Machines Corporation, Mark F Chadurjian, Eugene I Shkurko, F William McLaughlin, December 10, 2002: US06492211 (125 worldwide citation)

There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PN ...



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