1
Ulrich Klostermann
Juergen Zimmer, Ulrich Klostermann, Christian Alof: Magnetoresistive sensor element for sensing a magnetic field. Infineon Technologies, Eschweiler & Associates, February 24, 2009: US07495434 (9 worldwide citation)

A magnetoresistive sensor element has a first magnetic layer structure, a second magnetic layer structure, and a barrier layer. The resistance R1 of the first magnetic layer structure, the resistance R2 of the second magnetic layer structure and resistance-area product RA define a characteristic len ...


2
Dr. Elke Erben
Andreas Spitzer, Elke Erben: Method of manufacturing a dielectric layer and corresponding semiconductor device. Qimonds, Eschweiler & Associates, May 12, 2009: US07531405

A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than ...


3
Jonas Sundqvist
Bernd Hintze, Stephan Kudelka, Jonas Sundqvist: Method of producing a conductive layer including two metal nitrides. Qimonda, Eschweiler & Associates, May 12, 2009: US07531418

In a method for producing a conductive layer a substrate is provided. On the substrate, a layer includes at least two different metal nitrides. In one embodiment, on a surface of the substrate a first metal nitride layer is deposited, followed by a second metal nitride layer formed thereon. A third ...


4

5
William George En, Angela Hui, Minh Van Ngo: Methods for improving carrier mobility of PMOS and NMOS devices. Advanced Micro Devices, Eschweiler & Associates, June 3, 2003: US06573172 (172 worldwide citation)

Methods are described for fabricating semiconductor devices, in which a tensile film is formed over PMOS transistors to cause a compressive stress therein and a compressive film is formed over NMOS transistors to achieve a tensile stress therein, by which improved carrier mobility is facilitated in ...


6
Santosh K Yachareni, Kazuhiro Kurihara, Binh Q Le, Michael S C Chung: Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells. Advanced Micro Devices, Fujitsu, Eschweiler & Associates, April 9, 2002: US06370061 (125 worldwide citation)

The present invention relates to flash memory systems and methods to determine the threshold voltage of core cells. In one exemplary system, there is provided a method of characterizing the high end of the threshold voltage distribution of an array of programmed cells. In accordance with the inventi ...


7
Darlene Hamilton, Ed Hsia, Pau Ling Chen: Multi bit program algorithm. Spansion, Eschweiler & Associates, May 2, 2006: US07038950 (99 worldwide citation)

Methods of programming NEW data into unprogrammed bits of a group of memory cells is provided. The method applies an interactive programming algorithm that individually verifies and programs the NEW data, reference (REF) data, and existing or OLD data. OLD data is separately verified to a compensate ...


8
Pau Ling Chen, Michael A Van Buskirk, Yu Sun: Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge. Advanced Micro Devices, Eschweiler & Associates, March 4, 2003: US06529412 (97 worldwide citation)

A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line precharge and hold circuit which is operable to apply and maintain a source terminal voltage (e.g., about 0 volts, ground) to a bi ...


9
Fatima Bathul, Darlene Hamilton, Masato Horiike: Multi-level ONO flash program algorithm for threshold width control. Spansion, Eschweiler & Associates, October 31, 2006: US07130210 (87 worldwide citation)

Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in ...


10
Kazuhiro Kurihara, Santosh K Yachareni: Decoder apparatus and methods for pre-charging bit lines. Advanced Micro Devices, Fujitsu, Eschweiler & Associates, February 25, 2003: US06525969 (86 worldwide citation)

Methods and apparatus are disclosed for reading memory cells in a virtual ground memory core, wherein a memory cell is selected to be read and an adjacent memory cell is precharged so as to mitigate leakage current associated with the adjacent cell. Decoder circuitry and methods are disclosed for se ...



Click the thumbnails below to visualize the patent trend.