1
Christopher Pettey, Lawrence H Rubin: Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link. Banderacom, E Alan Davis, James W Huffman, July 15, 2003: US06594712 (105 worldwide citation)

An Infiniband channel adapter for performing direct data transfers between a PCI bus and an Infiniband link without double-buffering the data in system memory. A local processor programs the channel adapter to decode addresses in a range of the PCI bus address space dedicated to direct transfers. Wh ...


2
Ray Hsu: Method for detecting differences between graphical programs. National Instruments Corporation, Jeffrey C Hood, E Alan Davis, Conley Rose & Tayon, October 26, 1999: US05974254 (89 worldwide citation)

A method for detecting differences between two graphical programs is disclosed. The graphical programs include objects, preferably arranged as a user interface panel, including controls and indicators, and a block diagram, including graphical code function blocks connected together as a data flow pr ...


3
Glen O Sescila III, Brian K Odom, Kevin L Schultz: PCI bus to IEEE 1394 bus translator. National Instruments Corporation, Jeffrey C Hood, E Alan Davis, Conley Rose & Tayon, September 14, 1999: US05953511 (81 worldwide citation)

A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 139 ...


4
Ian Robert Davies, Gene Maine, Rex Weldon Vedder: Method for efficient inter-processor communication in an active-active RAID system using PCI-express links. Dot Hill Systems Corporation, E Alan Davis, James W Huffman, January 1, 2008: US07315911 (73 worldwide citation)

A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the h ...


5
Rodney E Hooker: Microprocessor with repeat prefetch instruction. IP First, E Alan Davis, James W Huffman, December 14, 2004: US06832296 (60 worldwide citation)

A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string instruction p ...


6
Keith E Diefendorff: Microprocessor with improved data stream prefetching. MIPS Technologies, E Alan Davis, James W Huffman, February 13, 2007: US07177985 (59 worldwide citation)

A microprocessor with multiple stream prefetch engines each executing a stream prefetch instruction to prefetch a complex data stream specified by the instruction in a manner synchronized with program execution of loads from the stream is provided. The stream prefetch engine stays at least a fetch-a ...


7
Kevin D Kissell: Integrated mechanism for suspension and deallocation of computational threads of execution in a processor. MIPS Technologies, E Alan Davis, James W Huffman, January 22, 2008: US07321965 (56 worldwide citation)

A microprocessor includes a core configured to concurrently execute instructions of a plurality of program threads and a yield instruction, included in the instruction set of the microprocessor. The yield instruction includes an opcode for instructing the microprocessor core to suspend issuing instr ...


8
Mark A Doucet, David L Panak: Point-to-multipoint wide area telecommunications network via atmospheric laser transmission through a remote optical router. Dominion Communications, E Alan Davis, Jeffrey C Conley Rose & Tayon Hood, July 28, 1998: US05786923 (56 worldwide citation)

A point-to-multipoint bi-directional wide area telecommunications network employing atmospheric optical communication. The network comprises a primary transceiver unit, a plurality of subscriber transceiver units and an optical router. The primary transceiver unit generates a first light beam on whi ...


9
Jeff D Washington, Paul F Austin: System and method for editing a control via direct graphical user interaction. National Instruments Corporation, Jeffrey C Hood, E Alan Davis, Conley Rose & Tayon, February 9, 1999: US05870088 (55 worldwide citation)

A method for editing an OLE control wherein changes may be made to the control in a direct graphically interactive manner. The user drags an icon representation of the control and drops the control onto a form of a container which supports OLE controls, such as Visual Basic. When the user drops the ...


10
Paul Andrew Ashmore, Dwight Oliver Lintz, Gene Maine, Victor Key Pecone, Rex Weldon Vedder: RAID controller using capacitor energy source to flush volatile cache data to non-volatile memory during main power outage. Dot Hill Systems Corporation, E Alan Davis, James W Huffman, May 19, 2009: US07536506 (43 worldwide citation)

A write-caching RAID controller is disclosed. The controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to storage devices when a main power source is supplying power to the RAID ...