61
Kammler Thorsten, Wieczorek Karsten, Lenski Markus: Method of forming a nickel silicide region in a doped silicon-containing semiconductor area. Advanced Micro Devices, DRAKE Paul S, May 21, 2004: WO/2004/042809

In highly sophisticated MOS transistors including nickel silicide portions (311) for reducing the silicon sheet resistance, nickel silicide stingers may lead to short circuits between the drain and source region and the channel region, thereby significantly lowering production yield. By substantiall ...


62
Lingunis Emmanuil H, Wong Nga Ching Alan, Haddad Sameer, Randolph Mark W, Ramsbey Mark T, Melik Martirosian Ashot, Runnion Edward F, He Yi: Pocket implant for complementary bit disturb improvement and charging improvement of sonos memory cell. Advanced Micro Devices, Lingunis Emmanuil H, Wong Nga Ching Alan, Haddad Sameer, Randolph Mark W, Ramsbey Mark T, Melik Martirosian Ashot, Runnion Edward F, He Yi, DRAKE Paul S, August 25, 2005: WO/2005/078791

A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer (608) is formed over a substrate (602) and a resist (614) is formed over the portion of the charge trapping dielectric layer (608). The resist (614) is ...


63
Phan Khoi A, Rangarajan Bharath, Singh Bhanwar: Multi-layer overlay measurement and correction technique for ic manufacturing. Advanced Micro Devices, Phan Khoi A, Rangarajan Bharath, Singh Bhanwar, DRAKE Paul S, September 15, 2005: WO/2005/086223

A system facilitating measurement and correction of overlay between multiple layers of a wafer (402) is disclosed. The system comprises an overlay target (406) that represents overlay between three or more layers of a wafer (402) and a measurement component (408) that determines overlay error existe ...


64
Garg Atul, Lai Siaw Kang: Method of improving operational speed of encryption engine. Advanced Micro Devices, Garg Atul, Lai Siaw Kang, DRAKE Paul S, October 27, 2005: WO/2005/101728

In the present method of implementing functioning of an encryption engine, a plurality of logic blocks (LB I - LB 32) are provided, each for running a function (F, G, H, I). Each function is run based on three variables (B, C, D), each of which may have a first or second value. The function is run w ...


65
Marxsen Gerd, Kramer Jens, Stoeckgen Uwe Gunter: A method and system for controlling the chemical mechanical polishing by using a sensor signal of a pad conditioner. Advanced Micro Devices, Marxsen Gerd, Kramer Jens, Stoeckgen Uwe Gunter, DRAKE Paul S, April 14, 2005: WO/2005/032763

In a system and a method, according to the present invention, a sensor signal, such as a motor current signal, from a drive assembly of a pad conditioning system is used to control a CMP system to compensate for a change in the conditions of consumables, thereby enhancing process stability.


66
Randolph Mark, Haddad Sameer, Thurgate Timothy, Fastow Richard: Memory cell array with staggered local inter-connect structure. Advanced Micro Devices, Randolph Mark, Haddad Sameer, Thurgate Timothy, Fastow Richard, DRAKE Paul S, April 28, 2005: WO/2005/038810

A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells ...


67
Zheng Wei, Randolph Mark: Recess channel flash architecture for reduced short channel effect. Advanced Micro Devices, Zheng Wei, Randolph Mark, DRAKE Paul S, April 28, 2005: WO/2005/038933

A memory cell with reduced short channel effects is described. A source region (54) and a drain region (56) are formed in a semiconductor substrate (58). A trench region (59) is formed between the source region and the drain region. A recessed channel region (52) is formed below the trench region, t ...


68
Chan Darin A, Chan Simon S, Hui Angela T: Method of forming planarized shallow trench isolation. Advanced Micro Devices, Chan Darin A, Chan Simon S, Hui Angela T, DRAKE Paul S, August 11, 2005: WO/2005/074023

Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill (25) with respect to the polish stop film (23) prior to removing the polish stop film (23). Embodiments include etching back a silicon oxide trench fill (25) to a depth of about 200 Å to about 1 ...


69
Mcgee William A, Gieseke Bruce Alan, Ognjen Milic Strkalj: Memory device and method of manufacture. Advanced Micro Devices, Mcgee William A, Gieseke Bruce Alan, Ognjen Milic Strkalj, DRAKE Paul S, August 18, 2005: WO/2005/076350

A memory cell (12) and a method for manufacturing the memory cell (12). The memory cell (12) is constructed so that it has a ratio of a dimension in the direction of the bit lines (164, 176) to a dimension in the direction of the word line (188) of less than one. The bit lines (164, 176) are formed ...


70
Pickett James K, Sander Benjamin Thomas, Lepak Kevin Michael: Data speculation based on addressing patterns identifying dual-purpose register. Advanced Micro Devices, Pickett James K, Sander Benjamin Thomas, Lepak Kevin Michael, DRAKE Paul S, August 12, 2004: WO/2004/068341

A system may include a memory file (136) and an execution core (124). The memory file (136) may include an entry (420) configured to store an addressing pattern (406) and a tag (408). If an addressing pattern of a memory operation matches the addressing pattern (406) stored in the entry (420), the m ...