1
Lyons Christopher F, Babcock Carl P, Kye Jongwook: Immersion lithographic process using a conforming immersion medium. Advanced Micro Devices, Lyons Christopher F, Babcock Carl P, Kye Jongwook, DRAKE Paul S, July 7, 2005: WO/2005/062128 (353 worldwide citation)

A method of making a device using a lithographic system (10) having a lens (32) from which an exposure pattern (24) is emitted. A conforming immersion medium (26) can be positioned between a photo resist layer (34) and the lens. The photo resist layer, which can be disposed over a wafer, and the len ...


2
Talbot Gerald R: Memory controller including a dual- mode memory interconnect. Advanced Micro Devices, Talbot Gerald R, DRAKE Paul S, May 8, 2008: WO/2008/054696 (13 worldwide citation)

A memory controller including a dual-mode memory interconnect includes an input/output (I/O) circuit including a plurality of input buffers and a plurality of output drivers. The I/O circuit may be configured to operate in one of a first mode and a second mode dependent upon a state of a mode select ...


3
Subramanian Ramkumar, Singh Bhanwar, Phan Khoi A: Use of supercritical fluid to dry wafer and clean lens in immersion lithography. Advanced Micro Devices, Spansion, Subramanian Ramkumar, Singh Bhanwar, Phan Khoi A, DRAKE Paul S, January 11, 2007: WO/2007/005362 (12 worldwide citation)

Disclosed are immersion lithography methods and systems involving irradiating a photoresist through a lens and an immersion liquid of an immersion lithography tool, the immersion liquid in an immersion space contacting the lens and the photoresist; removing the immersion liquid from the immersion sp ...


4
Too Seah Sun, Khan Mohammad, Hayward James, Diep Jacquana: Integrated circuit packaging. Advanced Micro Devices, Too Seah Sun, Khan Mohammad, Hayward James, Diep Jacquana, DRAKE Paul S, December 13, 2007: WO/2007/142721 (11 worldwide citation)

Various integrated circuit package elements are provided. In one aspect, an integrated circuit package device is provided that includes a lid (20) for covering an integrated circuit (12). The lid (20) has a convex surface (40) for applying pressure on the integrated circuit (12) when the Hd (20) is ...


5
Bill Colin S, Cai Wei Daisy: Temperature compensation of thin film diode voltage threshold in memory sensing circuit. Spansion, Bill Colin S, Cai Wei Daisy, DRAKE Paul S, September 28, 2006: WO/2006/102391 (7 worldwide citation)

Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit (408) and an array core (500) with a temperature variable select device (430). The array core (500) ca ...


6
Randolph Mark, Hamilton Darlene, Kornitz Roni: Methods and systems for high write performance in multi-bit flash memory devices. Spansion, Randolph Mark, Hamilton Darlene, Kornitz Roni, DRAKE Paul S, November 10, 2005: WO/2005/106891 (6 worldwide citation)

Methods and circuits are presented for performing high speed write (programming) operations in a dual-bit flash memory array. The method (200) includes, for example, erasing (204) a first and second bit of each cell in the array to a first state, programming (206) the first bit of each cell in the a ...


7
Sun Sey Ping, Brown David E: Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility. Advanced Micro Devices, Sun Sey Ping, Brown David E, DRAKE Paul S, November 24, 2005: WO/2005/112127 (5 worldwide citation)

The carrier mobility in transistor channel regions of Si-Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively (90) or high tensil ...


8
Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T: System and method for handling exceptional instructions in a trace cache based processor. Advanced Micro Devices, Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T, DRAKE Paul S, May 6, 2005: WO/2005/041024 (4 worldwide citation)

A system may include an instruction cache (106), a trace cache (160) including a plurality of trace cache entries (162), and a trace generator (170) coupled to the instruction cache (106) and the trace cache (160). The trace generator (170) may be configured to receive a group of instructions output ...


9
Gold Spencer M, Branover Alex, Cho Hanwoo, Nussbaum Sebastien: Automatic processor overclocking. Advanced Micro Devices, Gold Spencer M, Branover Alex, Cho Hanwoo, Nussbaum Sebastien, DRAKE Paul S, September 17, 2009: WO/2009/114141 (4 worldwide citation)

Processor overclocking techniques are disclosed. Upon automatically determining (310) that overclocking entry criteria are satisfied, one or more cores (230) are clocked (320) above their standard operation frequencies. The cores (230) may be overclocked until one or more exit criteria are satisfied ...


10
Yan John, Du Yong, Symmon Bruce E: Multi-chip module and method of manufacture. Spansion, Yan John, Du Yong, Symmon Bruce E, DRAKE Paul S, November 2, 2006: WO/2006/115649 (4 worldwide citation)

A multi-chip module (10) and a method for manufacturing the multi-chip module (10). A first semiconductor chip (40) is mounted to a support substrate (12) and a second semiconductor chip (50) is mounted to the first semiconductor chip (40). The second semiconductor chip (50) has a smaller dimension ...



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