1
Oh Kyong Kwon, Masashi Hashimoto, Satwinder Malhi, Eng C Born: Full wafer integrated circuit testing device. Texas Instruments Incorporated, James C Kesterson, Douglas A Sorensen, Richard L Donaldson, December 3, 1991: US05070297 (239 worldwide citation)

A full wafer integrated circuit testing device (10) tests integrated circuits (15) formed as a wafer in conjunction with a test control unit (40). Probe units (14) associate with respective integrated circuits (15). Probe tips (16) on probe units (14) communicate with respective pads (19) with the i ...


2
Mehrdad M Moslehi: Low-temperature in-situ dry cleaning process for semiconductor wafers. Texas Instruments Incorporated, Douglas A Sorensen, Richard L Donaldson, William E Hiller, February 18, 1992: US05089441 (233 worldwide citation)

A low-temperature (650.degree. C. to 800.degree. C.) in-situ dry cleaning process (FIG. 2) for removing native oxide (and other contaminants) from a semiconductor surface can be used with either multi-wafer or single-wafer semiconductor device manufacturing reactors. A wafer is contacted with a dry ...


3
Pallab K Chatterjee, Ashwin H Shah: Vertical DRAM cell and method. Texas Instruments Incorporated, Douglas A Sorensen, James T Comfort, Melvin Sharp, June 16, 1987: US04673962 (182 worldwide citation)

DRAM cells and arrays of cells on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. ...


4
Cesar M Garza, Monte A Douglas, Roland Johnson: Trilayer microlithographic process using a silicon-based resist as the middle layer. Texas Instruments Incorporated, Douglas A Sorensen, Rodney M Anderson, Melvin Sharp, January 2, 1990: US04891303 (114 worldwide citation)

A method for patterning an integrated circuit workpiece (10) includes forming a first layer (16) of organic material on the workpiece surface to a depth sufficient to allow a substantially planar outer surface (36) thereof. A second, polysilane-based resist layer (22) is spin-deposited on the first ...


5
Mehrdad M Moslehi: Method and apparatus for real-time wafer temperature measurement using infrared pyrometry in advanced lamp-heated rapid thermal processors. Texas Instruments Incorporated, Douglas A Sorensen, Rodney M Anderson, Melvin Sharp, September 11, 1990: US04956538 (113 worldwide citation)

A first and second pyrometer (26-28) are optically coupled by a light pipe (24) to a wafer (30) in an apparatus (10). The light pipe (24) passes through a shroud (16) of a heating lamp module (14). A computer (74) is interconnected to the pyrometers (26-28) and a lamp module power supply (80). A las ...


6
Wayne G Fisher: Integrated circuit planarization by mechanical polishing. Texas Instruments Incorporated, Douglas A Sorensen, Rodney M Anderson, Melvin Sharp, November 7, 1989: US04879258 (112 worldwide citation)

A process for planarizing the surface of a semiconductor wafer, after the wafer has been processed to form nonplanar topography layers on the blank, polished wafer, by mechanically removing material from this surface by abrasion until a desired planarity is attained. The mechanical planarization pre ...


7
Pallab K Chatterjee, Satwinder Malhi, William F Richardson: DRAM Cell with trench capacitor and vertical channel in substrate. Texas Instruments Incorporated, Douglas A Sorensen, Richard L Donaldson, May 4, 1993: US05208657 (111 worldwide citation)

A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transi ...


8
Gordon P Pollack, Mishel Matloubian, Ravishankar Sundaresan: Thin oxide sidewall insulators for silicon-over-insulator transistors. Texas Instruments Incorporated, James T Comfort, Melvin Sharp, Douglas A Sorensen, September 11, 1990: US04956307 (101 worldwide citation)

A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is the ...


9
Monte A Douglas: Trench etch process for a single-wafer RIE dry etch reactor. Texas Instruments Incorporated, Thomas W DeMond, Douglas A Sorensen, Melvin Sharp, November 15, 1988: US04784720 (99 worldwide citation)

A plasma dry etch process for trench etching in single slice RIE etch reactors wherein a selective sidewall passivation is accomplished to control the profile of the trench being etched. The process comprises methods of passivating the sidewall by passivation on a molecular scale and by passivation ...


10
Ashwin H Shah, James D Gallia, I Fay Wang, Shivaling S Mahant Shetti: Memory with redundancy. Texas Instruments Incorporated, Robert Groover III, Douglas A Sorensen, Melvin Sharp, July 15, 1986: US04601019 (92 worldwide citation)

A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally recei ...